AD7192 Analog Devices, AD7192 Datasheet - Page 25

• Manufacturer Part Number: AD7192
• Description: 4.8 kHz Ultra-Low Noise 24-Bit Sigma-Delta ADC with PGA
• Manufacturer: Analog Devices

Specifications of AD7192

• Resolution (bits): 24bit
• # Chan: 4
• Sample Rate: 4.8kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni,SE-Bip,SE-Uni
• Ain Range: ± (Vref/Gain)
• Adc Architecture: Sigma-Delta
• Pkg Type: SOP

ADC CIRCUIT INFORMATION
OVERVIEW
The AD7192 is an ultralow noise ADC that incorporates a Σ-Δ
modulator, a buffer, PGA, and on-chip digital filtering intended
for the measurement of wide dynamic range signals such as
those in pressure transducers, weigh scales, and strain gage
applications.
The part can be configured to have two differential inputs or
four pseudo differential inputs that can be buffered or unbuffered.
Figure 18 shows the basic connections required to operate the part.
FILTER, OUTPUT DATA RATE, AND SETTLING TIME
A Σ-Δ ADC consists of a modulator followed by a digital filter.
The AD7192 has two filter options: a sinc
filter. The filter is selected using the SINC3 bit in the mode
register. When the SINC3 bit is set to 0 (default value), the sinc
filter is selected. The sinc
set to 1.
At low output data rates (<1 kHz), the noise-free resolution is
comparable for the two filter types. However, at the higher
update rates, the sinc
The sinc
While the notch positions are not affected by the order of the
filter, the higher order filter has wider notches, which leads to
better rejection in the band (±1 Hz) around the notches. It also
gives better stop-band attenuation. The benefit of the sinc
is its lower settling time for the same output data rate.
Chop Disabled
The output data rate (the rate at which conversions are available
on a single channel when the ADC is continuously converting)
is equal to
4
filter also leads to better 50 Hz and 60 Hz rejection.
OUT–
4
filter gives better noise-free resolution.
3
IN+
IN–
filter is selected when the SINC3 bit is
5V
OUT+
3
REFIN1(–)
BPDSW
REFIN1(+)
AIN1
AIN2
AIN3
AIN4
AINCOM
filter and a sinc
AGND
MUX
AGND
Figure 18. Basic Connection Diagram
AGND
AV
DD
AV
3
4
AD7192
filter
DD
Rev. A | Page 25 of 40
4
SENSOR
TEMP
PGA
MCLK1 MCLK2
CIRCUITRY
where:
f
f
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the
mode register.
The output data rate can be programmed from 4.7 Hz to 4800 Hz;
that is, FS[9:0] can have a value from 1 to 1023.
The previous equation is valid for both the sinc
filters. The settling time for the sinc
and the settling time for the sinc
Figure 19 and Figure 20 show the frequency response of the sinc
filter and sinc
CLOCK
ADC
CLK
= master clock (4.92 MHz nominal).
is the output data rate.
f
t
t
DV
ADC
SETTLE
SETTLE
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
ADC
Σ-Δ
DD
0
Figure 19. Sinc
= f
0
DGND
P0/REFIN2(–) P1/REFIN2(+)
= 4/f
= 3/f
CLK
3
/(1024 × FS[9:0])
filter, respectively, for an output data rate of 50 Hz.
ADC
ADC
25
INTERFACE
CONTROL
SERIAL
LOGIC
REFERENCE
AND
4
Filter Response (50 Hz Output Data Rate)
DETECT
50
FREQUENCY (Hz)
3
75
DOUT/RDY
DIN
SCLK
CS
SYNC
P3
P2
filter is equal to
4
filter is equal to
100
3
125
and sinc
AD7192
150
4
4