AD9251 Analog Devices, AD9251 Datasheet - Page 34

• Manufacturer Part Number: AD9251
• Description: 14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9251

• Resolution (bits): 14bit
• # Chan: 2
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p,2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9251
Address
(Hex)
0x2A
0x2E
Digital Feature Control
0x100
0x101
MEMORY MAP REGISTER DESCRIPTIONS
For additional information about functions controlled in
Register 0x00 to Register 0xFF, see the
Note, Interfacing to High Speed ADCs via SPI.
Sync Control (Register 0x100)
Bits[7:3]—Reserved
Bit 2—Clock Divider Next Sync Only
If the master sync enable bit (Address 0x100, Bit 0) and the
clock divider sync enable bit (Address 0x100, Bit 1) are high,
Bit 2 allows the clock divider to sync to the first sync pulse it
receives and to ignore the rest. The clock divider sync enable
bit (Address 0x100, Bit 1) resets after it syncs.
Bit 1—Clock Divider Sync Enable
Bit 1 gates the sync pulse to the clock divider. The sync signal
is enabled when Bit 1 and Bit 0 are high and the device is
operating in continuous sync mode as long as Bit 2 of the
sync control is low.
Bit 0—Master Sync Enable
Bit 0 must be high to enable any of the sync functions.
Register
Name
Features
Output assign
Sync control
(global)
USR2
Bit 7
(MSB)
Open
Open
Open
Enable
OEB
Pin 47
(local)
AN-877
Bit 6
Open
Open
Open
Open
Application
Bit 5
Open
Open
Open
Open
Rev. A | Page 34 of 36
Open
Open
Open
Open
Bit 4
Open
Open
Open
Enable
GCLK
detect
Bit 3
USR2 (Register 0x101)
Bit 7—Enable OEB Pin 47
Normally set high, this bit allows Pin 47 to function as the
output enable. If it is set low, it disables Pin 47.
Bit 3—Enable GCLK Detect
Normally set high, this bit enables a circuit that detects encode
rates below about 5 MSPS. When a low encode rate is detected,
an internal oscillator, GCLK, is enabled ensuring the proper
operation of several circuits. If set low, the detector is disabled.
Bit 2—Run GCLK
This bit enables the GCLK oscillator. For some applications
with encode rates below 10 MSPS, it may be preferable to set
this bit high to supersede the GCLK detector.
Bit 0—Disable SDIO Pull-Down
This bit can be set high to disable the internal 30 kΩ pull-down
on the SDIO pin, which can be used to limit the loading when
many devices are connected to the SPI bus.
Open
Open
Clock
divider
next
sync
only
Run
GCLK
Bit 2
Bit 1
Open
Open
Clock
divider
sync
enable
Open
0 = ADC A
Bit 0
(LSB)
OR OE
(local)
1 = ADC B
(local)
Master
sync
enable
Disable
SDIO pull-
down
Default
Value
(Hex)
0x01
Ch A =
0x00
Ch B =
0x01
0x01
0x88
Comments
Disable the OR
pin for the
indexed
channel
Assign an ADC
to an output
channel
Enables
internal
oscillator for
clock rates <
5 MHz