AD6657 Analog Devices, AD6657 Datasheet - Page 21

• Manufacturer Part Number: AD6657
• Description: Quad IF Receiver
• Manufacturer: Analog Devices

Data Sheet
DIGITAL OUTPUTS
The AD6657 output drivers are configured to interface with
LVDS outputs using a DRVDD supply voltage of 1.8 V. The
output bits are DDR LVDS as shown in Figure 2. Applications
that require the ADC to drive large capacitive loads or large
fanouts may require external buffers or latches.
As described in Application Note AN-877, Interfacing to High
Speed ADCs via SPI, the data format can be selected for offset
binary or twos complement when using the SPI control.
TIMING
The AD6657 provides latched data with a latency of nine clock
cycles. Data outputs are available one propagation delay (t
after the rising edge of the clock signal.
Table 11. Output Data Format
Input (V)
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
Condition (V)
< −V
> +V
= −V
= 0
= +V
REF
REF
REF
REF
− 0.5 LSB
− 0.5 LSB
− 1.0 LSB
Offset Binary Output Mode
000 0000 0000
000 0000 0000
100 0000 0000
111 1111 1111
111 1111 1111
PD
)
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The length of the output data lines and the loads placed on
them should be minimized to reduce transients within the
AD6657. These transients can degrade converter dynamic
performance.
The lowest typical conversion rate of the AD6657 is 40 MSPS.
At clock rates below 40 MSPS, dynamic performance can degrade.
Data Clock Output (DCO)
The AD6657 provides a data clock output (DCO) signal intended
for capturing the data in an external register. The output data
for Channel A and Channel C is valid when DCO is high; the
output data for Channel B and Channel D is valid when DCO is
low. See Figure 2 for a graphical timing description.
Twos Complement Mode
100 0000 0000
100 0000 0000
000 0000 0000
011 1111 1111
011 1111 1111
AD6657