AD6642 Analog Devices, AD6642 Datasheet - Page 8

• Manufacturer Part Number: AD6642
• Description: Dual IF Receiver
• Manufacturer: Analog Devices

AD6642
TIMING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, f
otherwise noted.
Table 5.
Parameter
SYNC TIMING REQUIREMENTS
SPI TIMING REQUIREMENTS
Timing Diagrams
t
t
t
t
t
t
t
t
t
t
t
SSYNC
HSYNC
DS
DH
CLK
S
H
HIGH
LOW
EN_SDIO
DIS_SDIO
D10+AB (MSB)
D10–AB (MSB)
D0+AB (LSB)
D0–AB (LSB)
DCO+
DCO–
CLK+
CLK–
VIN
D10A
D0A
D10B
D0B
N – 1
Description
SYNC to rising edge of CLK setup time
SYNC to rising edge of CLK hold time
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to
an output relative to the SCLK falling edge
Time required for the SDIO pin to switch from an output to
an input relative to the SCLK rising edge
S
SYNC
= 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless
CLK+
t
CH
D10A
D0A
t
DCO
t
CL
D10B
D0B
t
N
PD
t
Figure 3. SYNC Input Timing Requirements
t
SSYNC
A
D10A
1/
D0A
t
f
SKEW
S
Figure 2. Data Output Timing
Rev. A | Page 8 of 32
D10B
D0B
N + 1
t
HSYNC
D10A
D0A
D10B
D0B
N + 2
D10A
D0A
N + 3
D10B
D0B
Min
2
2
40
2
2
10
10
10
10
D10A
D0A
D10B
N + 4
D0B
Typ
0.24
0.40
D10A
D0A
Max
D10B
N + 5
D0B
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns