AD9262 Analog Devices, AD9262 Datasheet - Page 20

• Manufacturer Part Number: AD9262
• Description: 16-Bit, 2.5 MHz/5 MHz/10 MHz, 30 MSPS to 160 MSPS Dual Continuous Time Sigma-Delta ADC
• Manufacturer: Analog Devices

Specifications of AD9262

• Resolution (bits): 16bit
• # Chan: 2
• Sample Rate: 160MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: CSP

AD9262
Table 11. Common Modulator Clock Multiplication Factors
CLK±
(MHz)
30.72
39.3216
52.00
61.44
76.80
78.00
78.6432
89.60
92.16
122.88
134.40
153.60
157.2864
Jitter Considerations
The aperture jitter requirements for continuous time Σ-Δ conver-
ters may be more forgiving than Nyquist rate converters. The
continuous time Σ-Δ architecture is an oversampled system
and to accurately represent the analog input signal to the ADC,
a large number of output samples must be averaged together. As
a result, the jitter contribution from each sample is root sum
squared, resulting in a more subtle impact on noise perfor-
mance as compared to Nyquist converters where aperture
jitter has a direct impact on each sampled output.
In the block diagram of the continuous time Σ-Δ modulator
(see Figure 37), the two building blocks most susceptible to
jitter are the quantizer and the DAC. The error introduced
through the sampling process is reduced by the loop gain and
shaped in the same way as the quantization noise and, therefore,
its effect can be neglected. On the contrary, the jitter error
associated with the DAC directly adds to the input signal, thus
increasing the in-band noise power and degrading the modulator
performance. The SNR degradation due to jitter can be
represented by the following equation.
where f
The SNR performance of the AD9262 remains constant within
the input bandwidth of the converter, from DC to 10 MHz.
Therefore, the minimal jitter specification is determined at the
highest input frequency. From the calculation, the aperture
jitter of the input clock must be no greater than 1 ps to achieve
optimal SNR performance.
SNR = −20 log (2πf
analog
is the analog input frequency and t
0x0A[5:0]
(PLLMULT)
42
32
25
21
17
17
16
15
14
10
10
8
8
analog
t
jitter_rms
f
(MHz)
1290.24
1258.29
1300.00
1290.24
1305.60
1326.00
1258.29
1344.00
1290.24
1228.80
1344.00
1228.80
1258.29
VCO
) dB
f
(MHz)
645.12
629.15
650.00
645.12
652.80
663.00
629.15
672.00
645.12
614.40
672.00
614.40
629.15
MOD
jitter_rms
is the jitter.
BW
(MHz)
10.08
9.83
10.16
10.08
10.20
10.36
9.83
10.50
10.08
9.60
10.50
9.60
9.83
Rev. A | Page 20 of 32
POWER DISSIPATION AND STANDBY MODE
The AD9262 power consumption can be further reduced by
configuring the chip in channel power-down, standby, or sleep
mode. The low power modes turn off internal blocks of the chip,
including the reference. As a result, the wake-up time is depen-
dent on the amount of circuitry that is turned off. Fewer internal
circuits that are powered down result in proportionally shorter
wake-up time. The low power modes are shown in Table 12.
In the standby mode, all clock related activity and the output
channels are disabled. Only the references and CMOS outputs
remain powered up to ensure a short recovery and link integr-
ity. During sleep mode, all internal circuits are powered down,
putting the device into its lowest power mode, and the CMOS
outputs are disabled.
Each ADC channel can be independently powered down or
both channels can be set simultaneously by writing to the
channel index, Register 0x05[1:0].
Table 12. Low Power Modes
Mode
Normal
Power-Down
Standby
Sleep
0x08[1:0]
0x0
0x1
0x2
0x3
Analog Circuitry
On
Off
Off
Off
Clock
On
On
Off
Off
Ref
On
On
On
Off