AD9266 Analog Devices, AD9266 Datasheet - Page 24

• Manufacturer Part Number: AD9266
• Description: 16-Bit, 20/40/65/80 MSPS, 1.8 V Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9266

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 1 V p-p,2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9266
BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST
The AD9266 includes a built-in test feature that is designed to
enable verification of the integrity of the datapath, as well as to
facilitate board-level debugging. A built-in self-test (BIST) feature
that verifies the integrity of the digital datapath of the AD9266
is included. Various output test options are also provided to place
predictable values on the outputs of the AD9266.
BUILT-IN SELF-TEST (BIST)
The BIST is a thorough test of the digital portion of the selected
AD9266 signal path. Perform the BIST test after a reset to ensure
that the part is in a known state. During BIST, data from an internal
pseudorandom noise (PN) source is driven through the digital
datapath, starting at the ADC block output. At the datapath
output, CRC logic calculates a signature from the data. The
BIST sequence runs for 512 cycles and then stops. Once
completed, the BIST compares the signature results with
a predetermined value. If the signatures match, the BIST sets Bit 0
of Register 0x24, signifying the test passed. If the BIST test failed,
Bit 0 of Register 0x24 is cleared. The outputs are connected during
this test, so the PN sequence can be observed as it runs. Writing
0x05 to Register 0x0E runs the BIST. This enables Bit 0 (BIST
enable) of Register 0x0E and resets the PN sequence generator,
Bit 2 (BIST INIT) of Register 0x0E. At the completion of the BIST,
Rev. 0 | Page 24 of 32
Bit 0 of Register 0x24 is automatically cleared. The PN sequence
can be continued from its last value by writing a 0 in Bit 2 of
Register 0x0E. However, if the PN sequence is not reset, the
signature calculation does not equal the predetermined value
at the end of the test. At that point, the user must rely on
verifying the output data.
OUTPUT TEST MODES
The output test options are described in Table 16 at Address 0x0D.
When an output test mode is enabled, the analog section of the
ADC is disconnected from the digital back end blocks and the
test pattern is run through the output formatting block. Some of
the test patterns are subject to output formatting, and some are
not. The PN generators from the PN sequence tests can be reset
by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be
performed with or without an analog signal (if present, the
analog signal is ignored), but they do require an encode clock.
For more information, see the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.