AD9284 Analog Devices, AD9284 Datasheet - Page 14

• Manufacturer Part Number: AD9284
• Description: 8-Bit, 250 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)
• Manufacturer: Analog Devices

Specifications of AD9284

• Resolution (bits): 8bit
• # Chan: 2
• Sample Rate: 250MSPS
• Interface: Par
• Analog Input Type: Diff-Bip,SE-Uni
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9284
CLOCK INPUT CONSIDERATIONS
For optimum performance, clock the AD9284 sample clock inputs,
CLK+ and CLK− with a differential signal. The signal is typically
ac-coupled into the CLK+ and CLK− pins via a transformer or
capacitors.
Clock Input Options
The AD9284 has a very flexible clock input structure. The clock
input can be an LVDS, LVPECL, or sine wave signal. Each configu-
ration that is described in this section applies to CLK+ and CLK−.
Figure 21 and Figure 22 show the two preferred methods for
clocking the AD9284. A low jitter clock source is converted
from a single-ended signal to a differential signal using either
an RF transformer or an RF balun. The back-to-back Schottky
diodes across the transformer/balun secondary limit clock
excursions into the AD9284 to approximately 0.8 V p-p
differential.
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the AD9284, while
preserving the fast rise and fall times of the signal that are
critical to low jitter performance.
CLOCK
CLOCK
INPUT
INPUT
50Ω
Figure 21. Transformer-Coupled Differential Clock
0.1µF
50Ω
Figure 22. Balun-Coupled Differential Clock
100Ω
1nF
1nF
ADT1-1WT, 1:1 Z
Mini-Circuits
0.1µF
XFMR
0.1µF
0.1µF
®
0.1µF
0.1µF
SCHOTTKY
HSM2822
SCHOTTKY
DIODES:
HSM2822
DIODES:
CLK+
CLK–
CLK+
CLK–
ADC
ADC
Rev. 0 | Page 14 of 24
CLOCK
CLOCK
CLOCK
CLOCK
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 23. The AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515/AD9516/AD9517
excellent jitter performance.
A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 24. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517
clock drivers offer excellent jitter performance.
DIGITAL OUTPUTS
Digital Output Enable Function ( OE )
The AD9284 has a flexible three-state ability for the digital output
pins. The three-state mode is enabled using the
OE is set to logic level high,
are placed into a high impedance state.
INPUT
INPUT
INPUT
INPUT
50kΩ
50kΩ
Figure 24. Differential LVDS Sample Clock
Figure 23. Differential PECL Sample Clock
50kΩ
50kΩ
0.1µF
0.1µF
0.1µF
0.1µF
PECL DRIVER
LVDS DRIVER
AD951x
AD951x
the output drivers for both data buses
240Ω
240Ω
100Ω
100Ω
0.1µF
0.1µF
0.1µF
0.1µF
clock drivers offer
OE
CLK+
CLK–
CLK+
CLK–
pin. When
ADC
ADC