AD9434 Analog Devices, AD9434 Datasheet - Page 23

• Manufacturer Part Number: AD9434
• Description: 12-Bit, 370 MSPS/500 MSPS, 1.8 V Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9434

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 500MSPS
• Interface: Par
• Analog Input Type: Diff-Bip
• Ain Range: 1.5 V p-p,Bip 0.75V
• Adc Architecture: Pipelined
• Pkg Type: CSP

There are three pins that define the serial port interface (SPI) to
this particular ADC. They are the SCLK/DFS, SDIO, and CSB
pins. The SCLK/DFS (serial clock) is used to synchronize the
read and write data presented to the ADC. The SDIO (serial
data input/output) is a dual-purpose pin that allows data to be
sent to and read from the internal ADC memory map registers.
The CSB is an active low control that enables or disables the
read and write cycles (see Table 9).
USING THE AD9434 TO REPLACE THE AD9230
The AD9434 can be used to replace the AD9230 in many
applications. In these designs, the user should consider these
important differences:
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•
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Table 9. Serial Port Pins
Mnemonic
SCLK
SDIO
CSB
The falling edge of the CSB, in conjunction with the rising edge
of the SCLK, determines the start of the framing. An example of
the serial timing and its definitions can be found in Figure 52
and Table 11.
During an instruction phase, a 16-bit instruction is transmitted.
Data then follows the instruction phase and is determined by
Pin 28 is a DNC (do not connect) on the AD9434, and
should be left floating. The reset functionality of the
AD9230
available through the SPI interface.
Pin 31 is the interface to the AD9434 reference circuit. It
can be used to monitor the internal reference or provide an
external reference voltage (nominally 0.5 V). If the internal
reference is used, then this pin can float. The RBIAS func-
tion of the AD9230 is not necessary with the AD9434.
The input voltage range of the AD9434 is nominally
1.5 V p-p, whereas the AD9230 input range is 1.25 V p-p.
is not available through an external pin, but is
Function
SCLK (serial clock) is the serial shift clock in.
SCLK is used to synchronize serial interface
reads and writes.
SDIO (serial data input/output) is a dual-purpose
pin. The typical role for this pin is an input and
output depending on the instruction being sent
and the relative position in the timing frame.
CSB (chip select) is an active low control that
gates the read and write cycles.
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the W0 and W1 bits, which is one or more bytes of data. All
data is composed of 8-bit words. The first bit of each individual
byte of serial data indicates whether this is a read or write com-
mand. This allows the serial data input/output (SDIO) pin to
change direction from an input to an output.
Data can be sent in MSB or in LSB first mode. MSB first is
default on power-up and can be changed by changing the
configuration register. For more information about this feature
and others, see the
High Speed ADCs via SPI at www.analog.com.
HARDWARE INTERFACE
The pins described in Table 9 comprise the physical interface
between the programming device of the user and the serial port
of the AD9434. The SCLK pin and the CSB pin function as
inputs when using the SPI interface. The SDIO pin is bidirec-
tional, functioning as an input during the write phase and as an
output during readback.
This interface is flexible enough to be controlled by either
PROMs or PIC® mirocontrollers as well. This provides the user
with an alternate method to program the ADC other than a SPI
controller.
If the user chooses not to use the SPI interface, some pins serve
a dual function and are associated with a specific function when
strapped externally to AVDD or ground during device power-
on. The Configuration Without the SPI section describes the
strappable functions supported on the AD9434.
CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers,
the SCLK/DFS pin can alternately serve as a standalone CMOS-
compatible control pin. In this mode, connect the CSB pin to
AVDD, which disables the serial port interface.
Table 10. Mode Selection
Mnemonic
SCLK/DFS
External
Voltage
AVDD
AGND
AN-877
Application Note, Interfacing to
Configuration
Twos complement enabled
Offset binary enabled
AD9434