AD9257 Analog Devices, AD9257 Datasheet - Page 24

• Manufacturer Part Number: AD9257
• Description: Octal, 14-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
• Manufacturer: Analog Devices

AD9257
Figure 59 shows an example of the LVDS output using the
ANSI-644 standard (default) data eye and a time interval error
(TIE) jitter histogram with trace lengths of less than 24 inches
on standard FR-4 material.
Figure 60 shows an example of trace lengths exceeding 24 inches
on standard FR-4 material. Note that the TIE jitter histogram
reflects the decrease of the data eye opening as the edge deviates
from the ideal position.
It is the responsibility of the user to determine if the waveforms
meet the timing budget of the design when the trace lengths exceed
24 inches. Additional SPI options allow the user to further increase
the internal termination (increasing the current) of all eight outputs
Table 10. Digital Output Coding
Input (V)
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
Less Than 24 Inches on Standard FR-4, External 100 Ω Far Termination Only
Figure 59. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
–100
–200
–300
–400
2.5k
2.0k
1.5k
1.0k
0.5k
400
300
200
100
0
0
EYE: ALL BITS
Condition (V)
< −VREF − 0.5 LSB
= −VREF
= 0
= +VREF − 1.0 LSB
> +VREF − 0.5 LSB
ULS: 7000:400354
Offset Binary Output Mode
00 0000 0000 0000
00 0000 0000 0000
10 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1111
Rev. 0 | Page 24 of 40
to drive longer trace lengths, which can be achieved by program-
ming Register 0x15. Even though this option produces sharper
rise and fall times on the data edges and is less prone to bit errors,
it also increases the power dissipation of the DRVDD supply.
The default format of the output data is twos complement. Table 10
shows an example of the output coding format. To change the
output data format to offset binary, see the Memory Map section.
Data from each ADC is serialized and provided on a separate
channel in DDR mode. The data rate for each serial stream is equal
to 14 bits times the sample clock rate, quantity divided by 2,
with a maximum of 455 Mbps (14 bits × 65 MSPS)/2 = 455 Mbps.
The lowest typical conversion rate is 10 MSPS. See the Memory
Map section for details on enabling this feature.
Greater Than 24 Inches on Standard FR-4, External 100 Ω Far Termination Only
Figure 60. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
–100
–200
–300
2.5k
2.0k
1.5k
1.0k
0.5k
300
200
100
0
0
EYE: ALL BITS
Twos Complement Mode
10 0000 0000 0000
10 0000 0000 0000
00 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1111
ULS: 7000/18200
Data Sheet