CLC5623IN National Semiconductor, CLC5623IN Datasheet - Page 13

• Manufacturer Part Number: CLC5623IN
• Description: IC AMP VIDEO TRIPLE 14-DIP
• Manufacturer: National Semiconductor

Specifications of CLC5623IN

• Applications: Current Feedback
• Number Of Circuits: 3
• -3db Bandwidth: 148MHz
• Slew Rate: 370 V/µs
• Current - Supply: 3.2mA
• Current - Output / Channel: 130mA
• Mounting Type: Through Hole
• Package / Case: 14-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *CLC5623IN

Application Division
Dual Supply Operation
The CLC5623 operates on dual supplies as well as single
supplies. The non-inverting and inverting configurations are
shown in Figure 5 and .
Feedback Resistor Selection
The feedback resistor, R
frequency response of a current feedback amplifier.
Optimum performance of the CLC5623, at a gain of +2V/V, is
achieved with R
1k
the Typical Performance sections illustrate the recom-
mended R
R
Within limits, R
response.
As a rule of thumb, if the recommended R
the bandwidth will be cut in half.
Unity Gain Operation
• Decrease R
• Increase R
f
FIGURE 5. Dual Supply Non-Inverting Configuration
V
V
V
V
provide the maximum bandwidth with minimal peaking.
bandwidth
bandwith
in
in
o
in
FIGURE 6. Dual Supply Inverting Configuration
for the PDIP package. The frequency response plots in
R
A
t
v
f
R
for several gains. These recommended values of
b
f
f
to roll off frequency response and compress
R
R
f
R
f
5
6
can be adjusted to optimize the frequency
5
6
g
to peak frequency response and extend
g
f
equal to 750
CLC5623
-
CLC5623
+
-
V
+
V
V
V
1/3
CC
EE
1/3
11
CC
EE
4
11
4
6.8 F
0.1 F
0.1 F
6.8 F
6.8 F
0.1 F
0.1 F
6.8 F
+
f
R
+
, affects the loop gain and
R
f
7
+
f
7
+
for the SOIC package and
(Continued)
V
Note: R
for the non-inverting input.
Select R
R
V
in
in
o
= R
f
V
V
is doubled, then
t
o
b
|| R
A
o
t
provides DC bias
to yield desired
v
g
.
DS015004-43
DS015004-44
1
R
R
g
f
13
The recommended R
(for the PDIP package). R
at the inverting node may require a slight increase in R
maintain a flat frequency response.
Load Termination
The CLC5623 can source and sink near equal amounts of
current. For optimum performance, the load should be tied to
V
Additional parasitics and limitations on decoupling in the
CLC5623IN combine to provide a lower level of performance
than the CLC5623IM. The specifications in the Electrical
Characteristics tables are based on the performance of the
DIP package (CLC5623IN). For optimum performance, use
the CLC5623IM (SOIC package). Proper supply decoupling
and board layout are critical factors for obtaining optimum
performance of the CLC5623IN. Board layout is less critical
for the SOIC package. Use the evaluation boards as a guide
to proper layout.
Figure 7 illustrates the frequency response versus output
amplitude for the CLC5623IM. Compare the Frequency
Response vs. V
section, with Figure 7 . Notice that gain flatness and
bandwidth improve when the SOIC package is used.
Figure 8 illustrates the channel matching performance of the
surface mount version of the CLC5623. Once again, the
surface mount package performs better. If optimum
performance is desired, use the surface mount version of the
CLC5623.
CM
.
1M
FIGURE 7. Frequency Response vs. V
A
V
V
SOIC Package
v
o
CC
= 2, R
=
= 5V
O
f
=750
plot, in the
f
for unit gain (+1V/V) operation is 750
Frequency (Hz)
g
10M
is left open. Parasitic capacitance
V
V
o
o
V
V
= 2.5V
= 1.5V
±
o
o
= 2V
= 1V
5V Typical Performance
pp
pp
pp
pp
100M
V
o
= 0.1V
DS015004-45
www.national.com
o
pp
f
to