CLC412AJE National Semiconductor, CLC412AJE Datasheet - Page 12

• Manufacturer Part Number: CLC412AJE
• Description: IC OP AMP VIDEO DUAL 8-SOIC
• Manufacturer: National Semiconductor

Specifications of CLC412AJE

• Applications: Current Feedback
• Number Of Circuits: 2
• -3db Bandwidth: 250MHz
• Slew Rate: 1300 V/µs
• Current - Supply: 10.2mA
• Current - Output / Channel: 70mA
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *CLC412AJE

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back track to figure the value of the feedback resistor, R
− R
desired frequency roll-off.
Circuit Layout
With all high frequency devices, board layouts with stray
capacitances have a strong influence over AC performance.
The CLC412 is no exception and its input and output pins
are particularly sensitive to the coupling of parasitic capaci-
tances (to AC ground) arising from traces or pads placed too
closely (
due to the frequency response peaking caused by these
parasitics, a small adjustment of the feedback resistor value
will serve to compensate the frequency response. Also, it is
very important to keep the parasitic capacitance across the
feedback resistor to an absolute minimum.
The performance plots in the data sheet can be reproduced
using the evaluation boards available from National. There
are two types of boards; the DIP (#730038) and SOIC
(#730036). The #730036 board uses all SMT parts for the
evaluation of the CLC412 in its surface mount package.
Either of these layouts can assist the designer in obtaining
the desired performance. In addition, the boards can serve
as an example layout for the final production printed circuit
board.
Care must also be taken with the CLC412’s layout in order to
achieve the best circuit performance, particularly channel-to-
channel isolation. The decoupling capacitors (both tantalum
and ceramic) must be chosen with good high frequency
characteristics to decouple the power supplies and the
physical placement of the CLC412’s external components is
critical. Grouping each amplifier’s external components with
their own ground connection and separating them from the
external components of the opposing channel with the maxi-
mum possible distance is recommended. The input (R
gain setting resistors (R
recommended that the ceramic decoupling capacitor (0.1µF
chip or radial-leaded with low ESR) should be placed as
closely to the power pins as possible.
Package Parasitics
In addition to the parasitic capacitances arising from the
board layout, each of the CLC412’s packages has its own
characteristic set of parasitic capacitances and inductances
causing frequency response variation from package to pack-
age as shown in the plot below labeled “Frequency Re-
sponse vs. Package Type”. Due to its much smaller size, the
CLC412AJE (8-pin SOIC) shows the least amount of peak-
ing.
in
(1 + R
<
Frequency Response vs. Package Type
0.1”) to power or ground planes. In some cases,
f
/R
g
). This new value of R
f
) are the most critical. It is also
f
will produce the
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in
) and
f
= Z
t
12
Matching Performance
With proper board layout, the AC performance match be-
tween the two CLC412’s amplifiers can be tightly controlled
as shown in Typical Performance plot labeled “Small-Signal
Channel Matching”.
The measurements were performed with SMT components
using the recommended value of feedback resistor of 634
at a gain of +2V/V. The pulse response plot labeled “Pulse
Matching” found below shows the group delay matching
between amplifiers of the CLC412. The circuit topology is
described in Figure 3 .
The CLC412’s amplifiers, built on the same die, provide the
advantage of having tightly matched DC characteristics. The
typical DC matching specifications of the CLC412 are:
Slew Rate and Settling Time
One of the advantages of current-feedback topology is an
inherently high slew rate which produces a wider full power
bandwidth. The CLC412 has a typical slew rate of 1300V/µs.
The required slew rate for a design can be calculated by the
following equation: SR = 2 fV
Careful attention to parasitic capacitances is critical to
achieving the best settling time performance. The CLC412
has a typical short term settling time of 0.05% of 12ns for a
Vio =
±
0.60mV, lbn =
Large Signal Pulse Response
FIGURE 3.
±
pk
0.25µA, lbi =
.
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±
1.5µA.
01272142