CLC411AJP National Semiconductor, CLC411AJP Datasheet - Page 9

• Manufacturer Part Number: CLC411AJP
• Description: IC OP AMP HI SPEED VIDEO 8-DIP
• Manufacturer: National Semiconductor

Specifications of CLC411AJP

• Applications: Current Feedback
• Number Of Circuits: 1
• -3db Bandwidth: 200MHz
• Slew Rate: 2300 V/µs
• Current - Supply: 11mA
• Current - Output / Channel: 70mA
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *CLC411AJP

Enable/Disable Operation
The disable feature allows the outputs of several CLC411
devices to be connected onto a common analog bus forming
a high speed analog multiplexer. When disabled, the output
and inverting inputs of the CLC411 become high imped-
ances. The disable pin has an internal pull up resistor which
is pulled up to an internal voltage, not to an external supply.
Thee CLC411 is enabled when pin 8 is left open or pulled up
to
CMOS logic devices are necessary to drive the disable pin.
For example, CMOS logic with V
proper operation over temperature. TTL voltage levels are
inadequate for controlling the disable feature.
For faster enable/disable operation than 15V CMOS logic
devices will allow, the circuit of Figure 5 is recommended. A
fast four transistor comparator, Figure 5 , interfaces between
the CLC411 DISABLE pin and several standard logic fami-
lies. This circuit has a differential input between the bases of
Q1 and Q2. As such it may be drive directly from differential
ECL logic, as in shown in Figure 6 . Single-ended logic
families may also be used by establishing an appropriate
threshold voltage on the V
Figure 7 and Figure 8 illustrate a single-enabled ECL and
TTL interface respectively. The Disable input, the base of
Q1, is driven above and below the threshold, V
Fastest switching speeds result when the differential voltage
between the bases of Q1 and Q2 is kept to less than one
+7V and disabled when grounded or pulled below +3V.
FIGURE 9. General Multiplexing Circuit
FIGURE 8. TTL Interface
th
input, the base of Q2.
DD
+7V will guarantee
th
.
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volt. Single-ended ECL, Figure 7 , maintains this desired
maximum differential input voltage. TTL and CMOS have
higher V
ensure the voltage applied between the bases of Q1 and Q2
does not cause excessive switching delays in the CLC411.
Under the above proscribed four transistor interface, all
variations were evaluated with approximately 1ns rise and
fall times which produced switching speeds equivalent to the
rated disable/enable switching times found in the CLC411
Electrical Characteristics table.
A general multiplexer configuration using several CLC411s is
illustrated in Figure 9 , where a typical 8-to-1 digital mux is
used to control the switching operation of the paralleled
CLC411s. Since break-before-make is a guaranteed speci-
fication of the CLC411 this configuration works nicely. Notice
the buffers used in driving the disable pins of the CLC411s.
These buffers may be 15V CMOS logic devises mentioned
previously or any variation of the four-transistor comparator
illustrated above.
Extending Input/Output Range with V
As can be seen in Figure 3 , the magnitude of the internal
regulated supply voltages is fixed by V
with
floating. CMIR (common mode input range) and VO (output
voltage range, no load) are specified under these conditions.
These parameters implicitly have OV as their midpoint, i.e.
the VO range is
An external voltage source can be applied to +V
range of the input/output voltages. For example, if it were
desired to move the positive VO range from +6V to a +9V
maximum in unipolar operation, Figure 10 , DC Parameters
as a Function of +V
supply and +V
point on the +VO
vertical line from this point intersecting the other lines in the
graph. The circuit voltages are the ordinates of these inter-
sections. For this example these points are shown in the
FIGURE 10. DC Parameters as a Function of +V
±
15V external supplies, +V
high
to V
r
voltages. Referring to Figure 10 , locate the
±
low
max
6V, centered at OV.
excursions. The circuit of Figure 8 will
line where the ordinate is +9V. Draw a
r
is used to determine the required
r
is nominally +9V when left
z
. In normal operation,
r
r
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to shift the
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r