SAM3X8C Atmel Corporation, SAM3X8C Datasheet - Page 1191
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SAM3X8C
Manufacturer Part Number
SAM3X8C
Description
Manufacturer
Atmel Corporation
- Current page: 1191 of 1465
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This bit is cleared when UOTGHS_HSTPIPIDR.TXSTPEC bit is written to one. This will disable the Transmitted IN Data
interrupt (UOTGHS_HSTPIPIMR.TXSTPE).
• UNDERFIE: Underflow Interrupt Enable
This bit is set when UOTGHS_HSTPIPIER.UNDERFIES bit is written to one. This will enable the Transmitted IN Data inter-
rupt (UOTGHS_HSTPIPIMR.UNDERFIE).
This bit is cleared when UOTGHS_HSTPIPIDR.UNDERFIEC bit is written to one. This will disable the Transmitted IN Data
interrupt (UOTGHS_HSTPIPIMR.UNDERFIE).
• TXOUTE: Transmitted OUT Data Interrupt Enable
This bit is set when UOTGHS_HSTPIPIER.TXOUTES bit is written to one. This will enable the Transmitted IN Data inter-
rupt (UOTGHS_HSTPIPIMR.TXOUTE).
This bit is cleared when UOTGHS_HSTPIPIDR.TXOUTEC bit is written to one. This will disable the Transmitted IN Data
interrupt (UOTGHS_HSTPIPIMR.TXOUTE).
• RXINE: Received IN Data Interrupt Enable
This bit is set when UOTGHS_HSTPIPIER.RXINES bit is written to one. This will enable the Transmitted IN Data interrupt
(UOTGHS_HSTPIPIMR.RXINE).
This bit is cleared when UOTGHS_HSTPIPIDR.RXINEC bit is written to one. This will disable the Transmitted IN Data
interrupt (UOTGHS_HSTPIPIMR.RXINE).
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
SAM3X/A
SAM3X/A
1191
1191
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