SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 228
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SAM9XE512
Manufacturer Part Number
SAM9XE512
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9XE128.pdf
(860 pages)
4.SAM9XE128.pdf
(48 pages)
Specifications of SAM9XE512
Flash (kbytes)
512 Kbytes
Pin Count
217
Max. Operating Frequency
180 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
6
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.65 to 1.95
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9260 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9XE128 PDF datasheet #3
- SAM9XE128 PDF datasheet #4
- Current page: 228 of 290
- Download datasheet (5Mb)
Signal Descriptions
A.6
A-8
Debug signals
The debug signals are shown in Table A-6.
Name
DBGIR[3:0]
TAP controller
instruction register
DBGnTRST
Not test reset
DBGnTDOEN
Not DBGTDO
enable
DBGSCREG[4:0]
DBGSDIN
Output boundary
scan serial input
data
DBGSDOUT
Input boundary
scan serial output
data
DBGTAPSM[3:0]
TAP controller state
machine
DBGTCKEN
DBGTDI
DBGTDO
DBGTMS
Copyright © 2000 ARM Limited. All rights reserved.
Direction
Output
Input
Output
Output
Output
Input
Output
Input
Input
Output
Input
Description
These four bits reflect the current instruction loaded
into the TAP controller instruction register. These bits
change when the TAP state machine is in the
UPDATE-IR state.
This is the active LOW reset signal for the
EmbeddedICE internal state. This signal is a
level-sensitive asynchronous reset input.
When LOW, this signal denotes that serial data is
being driven out on the DBGTDO output.
DBGnTDOEN is usually used as an output enable
for a DBGTDO pin in a packaged part.
These five bits reflect the ID number of the scan chain
currently selected by the TAP Scan Chain Register
controller. These bits change when the TAP state
machine is in the UPDATE-DR state.
This signal contains the serial data to be applied to an
external scan chain.
This is the serial data out of an external scan chain.
When an external boundary scan chain is not
connected, this input must be tied LOW.
This bus reflects the current state of the TAP
controller state machine.
Synchronous enable for debug logic accessed using
the JTAG interface.
Test data input to the debug logic.
Output from the debug logic.
Test mode select for the TAP controller.
Table A-6 Debug signals
ARM DDI 0165B
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