SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 17

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

6.2.2
6.2.3
6438GS–ATARM–13-Jul-11
Matrix Slaves
Masters to Slaves Access
Each Slave has its own arbiter, thus allowing a different arbitration per Slave to be programmed.
Table 6-2.
All the Masters can normally access all the Slaves. However, some paths do not make sense,
such as allowing access from the Ethernet MAC to the internal peripherals. Thus, these paths
are forbidden or simply not wired, and shown “-” in the following tables.
The four DDR ports are connected differently according to the application device.
The user can disable the DDR multi-port in the DDR multi-port Register (bit DDRMP_DIS) in the
Chip Configuration User Interface.
Slave 0
Slave 1
Slave 2
Slave 3
Slave 4
Slave 5
Slave 6
Slave 7
• When the DDR multi-port is enabled (DDRMP_DIS=0), the ARM instruction and data are
• When the DDR multi-port is disabled (DDRMP_DIS=1), DDR Port 1 is dedicated to the LCD
respectively connected to DDR Port 0 and DDR Port 1. The other masters share DDR Port 2
and DDR Port 3.
controller. The remaining masters share DDR Port 2 and DDR Port 3.
List of Bus Matrix Slaves
Internal SRAM
Internal ROM
USB OHCI
USB EHCI
UDP High Speed RAM
LCD User Interface
DDR Port 0
DDR Port 1
DDR Port 2
DDR Port 3
External Bus Interface
Internal Peripherals
SAM9G45
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