SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 37

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

10.11 LCD Controller (LCDC)
10.12 Ethernet 10/100 MAC (EMAC)
11053AS–ATARM–27-Jul-11
• One Master
• Up to 266MHz input clock
• 384-byte Asynchronous Output FIFO
• One Background Layer
• One High End Overlay Layer, YUV Full planar, 4.2.0, 4.2.2 packed
• One Overlay RGB
• One Hardware cursor with user-defined size
• Up to 24 bits per Pixel in TFT Mode
• Dithering for 12bpp, 16bpp and 18bpp modes
• LUT for 1bpp, 2bpp, 4bpp and 8bpp
• Resolution Up to 2048x2048 pixels
• Supported formats:
• alpha blending, color conversion, rotation
• scaling up to 800x600 pixels
• supports RMII Mode only
• Compatibility with IEEE Standard 802.3
• 10 and 100 Mbits per second data throughput capability
• Full- and half-duplex operations
• Register Interface to address, data, status and control registers
• DMA Interface, operating as a master on the Memory Controller
• Interrupt generation to signal receive and transmit completion
• 128-byte transmit and 128-byte receive FIFOs
• Automatic pad and CRC generation on transmitted frames
• Address checking logic to recognize four 48-bit addresses
• Support promiscuous mode where all valid frames are copied to memory
• Support physical layer management through MDIO interface
• Support Wake On Lan: The receiver supports Wake on LAN by detecting the following events
on incoming receive frames:
– RGB: 444 (12bpp), 565 (16bpp), 666 (18bpp), 888 (24bpp and packed 24bpp)
– Transparency + RGB: 1555 (16bpp), 1666 (19bpp and packed 19bpp), 1888 (25bpp)
– Alpha + RGB or RGB + Alpha: 4444 (16bpp), 8888 (32bpp)
– Magic packet
– ARP request to the device IP address
– Specific address 1 filter match
– Multicast hash filter match
SAM9G35
37