SAM9G15 Atmel Corporation, SAM9G15 Datasheet - Page 187
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SAM9G15
Manufacturer Part Number
SAM9G15
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G15.pdf
(1211 pages)
5.SAM9G15.pdf
(45 pages)
Specifications of SAM9G15
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
6
Lin
4
Ssc
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G15 PDF datasheet #4
- SAM9G15 PDF datasheet #5
- Current page: 187 of 248
- Download datasheet (2Mb)
12.1.2
ARM DDI0198D
Static power management (leakage control)
EDBGRQ
nIRQ
nFIQ
When the ARM926EJ-S has entered a low-power state, all of the main internal clocks
are stopped, including the clock for the ARM9EJ-S core. However, the ARM9EJ-S is
active if DBGTCKEN is asserted. This enables values to be written in the ARM9EJ-S
debug control register so that a debugger can force an exit from wait for interrupt mode.
This means that you can safely stop the ARM926EJ-S CLK if STANDBYWFI is
HIGH and DBGTCKEN is LOW.
Figure 12-2 shows the recommended logic for stopping the main ARM926EJ-S clock
during wait for interrupt.
The nature of the nFIQ, nIRQ, and EDBGRQ signals enables them to be registered
prior to being used in the gating logic. DBGTCKEN must be used combinationally to
maintain the relationship between the ARM926EJ-S JTAG logic and the RTCK signal
used by the debugger. See the ARM9EJ-S Technical Reference Manual for details of
how DBGTCKEN is generated and used.
The ARM926EJ-S design is partitioned so that the SRAM blocks that are used for the
caches and the MMU can be powered down under certain conditions.
Cache RAMs
The RAMs for either of the caches can be safely powered down if the respective cache
has been disabled (using CP15 control register c1) and it contains no valid entries.
While a cache is disabled, only explicit CP15 operations can cause the cache RAMs to
be accessed (c7 cache maintenance operations). These instructions must not be
executed while any of the cache RAMs are powered down. If any of the RAMs for a
cache have been powered down, then they must be powered up prior to re-enabling the
relevant cache.
Copyright © 2001-2003 ARM Limited. All rights reserved.
Figure 12-2 Logic for stopping ARM926EJ-S clock during wait for interrupt
FCLK = Free running clock
CLK = Clock supplied to ARM926EJ-S macrocell
FCLK
DBGTCKEN
STANDBYWFI
FCLK
HRESETn
RST
EN
Power Management
CLK
12-3
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