SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 26
SAM9263
Manufacturer Part Number
SAM9263
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.SAM9260.pdf
(290 pages)
4.SAM9261.pdf
(248 pages)
5.SAM9263.pdf
(1109 pages)
6.SAM9263.pdf
(51 pages)
Specifications of SAM9263
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Can
1
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
96
Self Program Memory
NO
External Bus Interface
2
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
8.2.1.2
8.2.2
8.2.3
26
AT91SAM9263
Static Memory Controller
SDRAM Controller
External Bus Interface 1
• Integrates three External Memory Controllers:
• Additional logic for NAND Flash
• Optional Full 32-bit External Data Bus
• Up to 23-bit Address Bus (up to 8 Mbytes linear)
• Up to 3 Chip Selects, Configurable Assignment:
• Allows supporting an external Frame Buffer for the embedded LCD Controller without
• 8-, 16- or 32-bit Data Bus
• Multiple Access Modes supported
• Multiple device adaptability
• Multiple Wait State Management
• Slow Clock mode supported
• Supported devices
• Numerous configurations supported
• Programming facilities
impacting processor performance.
– Static Memory Controller
– SDRAM Controller
– ECC Controller
– Static Memory Controller on NCS0
– SDRAM Controller or Static Memory Controller on NCS1
– Static Memory Controller on NCS2, Optional NAND Flash support
– Byte Write or Byte Select Lines
– Asynchronous read in Page Mode supported (4- up to 32-byte page size)
– Compliant with LCD Module
– Control signals programmable setup, pulse and hold time for each Memory Bank
– Programmable Wait State Generation
– External Wait Request
– Programmable Data Float Time
– Standard and Low-power SDRAM (Mobile SDRAM)
– 2K, 4K, 8K Row Address Memory Parts
– SDRAM with two or four Internal Banks
– SDRAM with 16- or 32-bit Data Path
– Word, half-word, byte access
– Automatic page break when Memory Boundary has been reached
– Multibank Ping-pong Access
– Timing parameters specified by software
– Automatic refresh operation, refresh rate is programmable
6249HS–ATARM–27-Jul-09