SAM9260 Atmel Corporation, SAM9260 Datasheet - Page 17

• Manufacturer Part Number: SAM9260
• Manufacturer: Atmel Corporation

Specifications of SAM9260

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 210 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 7
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

7.2.1
7.2.2
7.2.3
6221KS–ATARM–17-May-11
Matrix Masters
Matrix Slaves
Master to Slave Access
The Bus Matrix of the SAM9260 manages six Masters, which means that each master can per-
form an access concurrently with others, according the slave it accesses is available.
Each Master has its own decoder that can be defined specifically for each master. In order to
simplify the addressing, all the masters have the same decodings.
Table 7-1.
Each Slave has its own arbiter, thus allowing a different arbitration per Slave to be programmed.
Table 7-2.
All the Masters can normally access all the Slaves. However, some paths do not make sense,
such as allowing access from the Ethernet MAC to the Internal Peripherals. Thus, these paths
are forbidden or simply not wired, and shown “-” in the following table.
Table 7-3.
Master 0
Master 1
Master 2
Master 3
Master 4
Master 5
Slave 0
Slave 1
Slave 2
Slave 3
Slave 4
• Boot Mode Select
• Remap Command
0
– Non-volatile Boot Memory can be internal or external
– Selection is made by BMS pin sampled at reset
– Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory
– Allows Handling of Dynamic Exception Vectors
Internal SRAM
Master
Slave
4 KBytes
List of Bus Matrix Masters
List of Bus Matrix Slaves
SAM9260 Masters to Slaves Access
Internal SRAM0 4 KBytes
Internal SRAM1 4 KBytes
Internal ROM
USB Host User Interface
External Bus Interface
Internal Peripherals
ARM926
ARM926 Data
PDC
USB Host DMA
ISI Controller
Ethernet MAC
Instruction &
ARM926
0 & 1
Data
X
™
Instruction
Peripheral
Controller
DMA
2
X
USB Host
Controller
X
3
Controller
ISI
4
X
SAM9260
Ethernet
MAC
X
5
17