SAM7XC128 Atmel Corporation, SAM7XC128 Datasheet - Page 39

• Manufacturer Part Number: SAM7XC128
• Manufacturer: Atmel Corporation

Specifications of SAM7XC128

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 55 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 62
• Ext Interrupts: 62
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 3
• Can: 1
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Resolution (bits): No
• Temp. Sensor: No
• Crypto Engine: AES/DES
• Sram (kbytes): 32
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

10.13 USB Device Port
10.14 CAN Controller
10.15 128-bit Advanced Encryption Standard
6209DS–ATARM–17-Feb-09
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• USB V2.0 full-speed compliant,12 Mbits per second
• Embedded USB V2.0 full-speed transceiver
• Embedded 1352-byte dual-port RAM for endpoints
• Six endpoints
• Suspend/resume logic
• Compliant with FIPS Publication 197, Advanced Encryption Standard (AES)
• 128-bit (AT91SAM7XC256/128) or 128-bit/192-bit/256-bit (AT91SAM7XC512) Cryptographic
• 12-clock Cycles Encryption/Decryption Processing Time (AT91SAM7XC256/128)
• 12/13/14-clock Cycles Encryption/Decryption Processing Time (AT91SAM7XC512)
• Support of the Five Standard Modes of Operation specified in the NIST Special Publication
Key
800-38A:
Fully compliant with CAN 2.0A and 2.0B
Bit rates up to 1Mbit/s
Eight object oriented mailboxes each with the following properties:
– Endpoint 0: 8 bytes
– Endpoint 1 and 2: 64 bytes ping-pong
– Endpoint 3: 64 bytes
– Endpoint 4 and 5: 256 bytes ping-pong
– Ping-pong Mode (two memory banks) for bulk endpoints
– CAN Specification 2.0 Part A or 2.0 Part B Programmable for each Message
– Object configurable to receive (with overwrite or not) or transmit
– Local tag and mask filters up to 29-bit identifier/channel
– 32-bit access to data registers for each mailbox data object
– Uses a 16-bit time stamp on receive and transmit message
– Hardware concatenation of ID unmasked bitfields to speedup family ID processing
– 16-bit internal timer for time stamping and network synchronization
– Programmable reception buffer length up to 8 mailbox objects
– Priority management between transmission mailboxes
– Autobaud and listening mode
– Low power mode and programmable wake-up on bus activity or by the application
– Data, remote, error and overload frame handling
– Electronic Codebook (ECB)
– Cipher Block Chaining (CBC)
– Cipher Feedback (CFB)
– Output Feedback (OFB)
AT91SAM7XC512/256/128
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