SAM7SE256 Atmel Corporation, SAM7SE256 Datasheet - Page 210
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SAM7SE256
Manufacturer Part Number
SAM7SE256
Description
Manufacturer
Atmel Corporation
Specifications of SAM7SE256
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
48 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
88
Ext Interrupts
88
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Signal Description
A-4
Name
BL[3:0]
Byte latch control
BREAKPT
Breakpoint
BUSDIS
Bus disable
BUSEN
Data bus configuration
COMMRX
Communications channel receive
COMMTX
Communications channel transmit
CPA
Coprocessor absent
Copyright © 1994-2001. All rights reserved.
Type
IC
IC
O4
IC
O4
O4
IC
Description
The values on the data bus are latched on the falling edge of MCLK
when these signals are HIGH. For most designs these signals must be tied
HIGH.
A conditional request for the processor to enter debug state is made by
placing this signal HIGH.
If the memory access at that time is an instruction fetch, the processor
enters debug state only if the instruction reaches the execution stage of
the pipeline.
If the memory access is for data, the processor enters debug state after the
current instruction completes execution. This allows extension of the
internal breakpoints provided by the EmbeddedICE Logic.
See Behavior of the program counter during debug on page B-29 for
details on the use of this signal.
When INTEST is selected on scan chain 0, 4, or 8 this is HIGH. It can be
used to disable external logic driving onto the bidirectional data bus
during scan testing. This signal changes after the falling edge of TCK.
A static configuration signal that selects whether the bidirectional data
bus (D[31:0]) or the unidirectional data busses (DIN[31:0] and
DOUT[31:0]) are used for transfer of data between the processor and
memory.
When BUSEN is LOW, D[31:0] is used; DOUT[31:0] is driven to a
value of zero, and DIN[31:0] is ignored, and must be tied LOW.
When BUSEN is HIGH, DIN[31:0] and DOUT[31:0] are used; D[31:0]
is ignored and must be left unconnected.
See Chapter 3 Memory Interface for details on the use of this signal.
When the communications channel receive buffer is full this is HIGH.
This signal changes after the rising edge of MCLK.
See Debug Communications Channel on page 5-16 for more
information.
When the communications channel transmit buffer is empty this is
HIGH.
This signal changes after the rising edge of MCLK.
See Debug Communications Channel on page 5-16 for more
information.
Placed LOW by the coprocessor if it is capable of performing the
operation requested by the processor.
Table A-3 Signal Descriptions (continued)
ARM DDI 0029G
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