SAM7S512 Atmel Corporation, SAM7S512 Datasheet - Page 25
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SAM7S512
Manufacturer Part Number
SAM7S512
Description
Manufacturer
Atmel Corporation
Specifications of SAM7S512
Flash (kbytes)
512 Kbytes
Pin Count
64
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
32
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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1.1.2
ARM DDI 0029G
Memory access
During normal operation, while one instruction is being executed, its successor is being
decoded, and a third instruction is being fetched from memory.
The program counter points to the instruction being fetched rather than to the instruction
being executed. This is important because it means that the Program Counter (PC)
value used in an executing instruction is always two instructions ahead of the address.
The ARM7TDMI core has a Von Neumann architecture, with a single 32-bit data bus
carrying both instructions and data. Only load, store, and swap instructions can access
data from memory.
Data can be:
•
•
•
Words must be aligned to 4-byte boundaries. Halfwords must be aligned to 2-byte
boundaries.
8-bit (bytes)
16-bit (halfwords)
32-bit (words).
Copyright © 1994-2001. All rights reserved.
Execute
Decode
Fetch
Instruction fetched from memory
Decoding of registers used in
instruction
Register(s) read from register bank
Perform shift and ALU operations
Write register(s) back to register bank
Figure 1-1 Instruction pipeline
Introduction
1-3
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