SAM3U4C Atmel Corporation, SAM3U4C Datasheet - Page 26
SAM3U4C
Manufacturer Part Number
SAM3U4C
Description
Manufacturer
Atmel Corporation
Specifications of SAM3U4C
Flash (kbytes)
256 Kbytes
Pin Count
100
Max. Operating Frequency
96 MHz
Cpu
Cortex-M3
# Of Touch Channels
28
Hardware Qtouch Acquisition
No
Max I/o Pins
57
Ext Interrupts
57
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
4
Twi (i2c)
1
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
50
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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7. Processor and Architecture
7.1
7.2
7.3
26
ARM Cortex-M3 Processor
APB/AHB Bridges
Matrix Masters
SAM3U Series
Even in all low power modes, asserting the pin will automatically start-up the chip and erase the
Flash.
The SAM3U product embeds two separated APB/AHB bridges:
This architecture enables to make concurrent accesses on both bridges.
All the peripherals are on the low-speed bridge except SPI, SSC and HSMCI.
The UART,
channels for the Peripheral DMA Channels (PDC). These peripherals can not use the DMA
Controller.
The high speed bridge regroups the SSC, SPI and HSMCI. These three peripherals do not have
PDC channels but can use the DMA with the internal FIFO for Channel buffering.
Note that the peripherals of the two bridges are clocked by the same source: MCK.
The Bus Matrix of the SAM3U device manages 5 masters, which means that each master can
perform an access concurrently with others to an available slave.
Each master has its own decoder and specifically defined bus. In order to simplify the address-
ing, all the masters have the same decoding.
Table 7-1.
Master 0
Master 1
Master 2
Master 3
Master 4
• Version 2.0
• Thumb-2 (ISA) subset consisting of all base Thumb-2 instructions, 16-bit and 32-bit.
• Harvard processor architecture enabling simultaneous instruction fetch with data load/store.
• Three-stage pipeline.
• Single cycle 32-bit multiply.
• Hardware divide.
• Thumb and Debug states.
• Handler and Thread modes.
• Low latency ISR entry and exit.
• low speed bridge
• high speed bridge
10-bit ADC (ADC), 12-bit ADC (ADC12B)
List of Bus Matrix Masters
Cortex-M3 Instruction/Data
Cortex-M3 System
Peripheral DMA Controller (PDC)
USB Device High Speed DMA
DMA Controller
, TWI0-1, USART0-3, PWM have dedicated
6430E–ATARM–29-Aug-11
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