SAM3U1E Atmel Corporation, SAM3U1E Datasheet - Page 49

• Manufacturer Part Number: SAM3U1E
• Manufacturer: Atmel Corporation

Specifications of SAM3U1E

• Flash (kbytes): 64 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 57
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 5
• Twi (i2c): 2
• Uart: 5
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 20
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

12.7
6430ES–ATARM–22-Aug-11
Pulse Width Modulation Controller (PWM)
• Each channel is user-configurable and contains:
• Two global registers that act on all three TC Channels
• 4 channels, one 16-bit counter per channel
• Common clock generator, providing Thirteen Different Clocks
• Independent channel programming
• Synchronous Channel mode
• Connection to one PDC channel
• Two independent event lines which can send up to 8 triggers on ADC within a period
• Four programmable Fault Inputs providing asynchronous protection of outputs
– Pulse Generation
– Delay Timing
– Pulse Width Modulation
– Up/Down Capabilities
– Quadrature Decoder Logic
– Three external clock inputs
– Five internal clock inputs
– Two multi-purpose input/output signals
– A Modulo n counter providing eleven clocks
– Two independent Linear Dividers working on modulo n counter outputs
– High Frequency Asynchronous clocking mode
– Independent Enable Disable Commands
– Independent Clock Selection
– Independent Period and Duty Cycle, with Double Buffering
– Programmable selection of the output waveform polarity
– Programmable center or left aligned output waveform
– Independent Output Override for each channel
– Independent complementary Outputs with 12-bit dead time generator for each
– Independent Enable Disable Commands
– Independent Clock Selection
– Independent Period and Duty Cycle, with Double Buffering
– Synchronous Channels share the same counter
– Mode to update the synchronous channels registers after a programmable number
– Offers Buffer transfer without Processor Intervention, to update duty cycle of
channel
of periods
synchronous channels
SAM3U Series
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