SAM3S1C Atmel Corporation, SAM3S1C Datasheet - Page 142
SAM3S1C
Manufacturer Part Number
SAM3S1C
Description
Manufacturer
Atmel Corporation
Specifications of SAM3S1C
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
64 MHz
Cpu
Cortex-M3
# Of Touch Channels
39
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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10.18.5
10.18.5.1
10.18.5.2
10.18.5.3
10.18.5.4
142
ISB
SAM3S
ISB
Syntax
Operation
Condition flags
Examples
; Instruction Synchronisation Barrier
Instruction Synchronization Barrier.
where:
cond
ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so that
all instructions following the ISB are fetched from memory again, after the ISB instruction has
been completed.
This instruction does not change the flags.
ISB{cond}
is an optional condition code, see
“Conditional execution” on page
6500C–ATARM–8-Feb-11
84.
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