SAM3N4C Atmel Corporation, SAM3N4C Datasheet - Page 437
SAM3N4C
Manufacturer Part Number
SAM3N4C
Description
Manufacturer
Atmel Corporation
Specifications of SAM3N4C
Flash (kbytes)
256 Kbytes
Pin Count
100
Max. Operating Frequency
48 MHz
Cpu
Cortex-M3
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Quadrature Decoder Channels
2
Usb Speed
No
Usb Interface
No
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
24
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Figure 27-7.
11011A–ATARM–04-Oct-10
11011A–ATARM–04-Oct-10
(from master)
(from slave)
TXEMPTY
NPCS0
SPCK
TDRE
MOSI
RDRF
MISO
SPI_TDR
Write in
Status Register Flags Behavior
Figure 27-7
Transmission Register Empty (TXEMPTY) status flags behavior within the SPI_SR (Status Reg-
ister) during an 8-bit data transfer in fixed mode and no Peripheral Data Controller involved.
Figure 27-8
of TX buffer (ENDTX), RX Buffer Full (RXBUFF) and TX Buffer Empty (TXBUFE) status flags
behavior within the SPI_SR (Status Register) during an 8-bit data transfer in fixed mode with the
Peripheral Data Controller involved. The PDC is programmed to transfer and receive three data.
The next pointer and counter are not used. The RDRF and TDRE are not shown because these
flags are managed by the PDC when using the PDC.
MSB
1
MSB
shows Transmit Data Register Empty (TDRE), Receive Data Register (RDRF) and
shows Transmission Register Empty (TXEMPTY), End of RX buffer (ENDRX), End
2
6
6
3
5
5
4
4
4
5
3
3
6
6
2
2
7
1
1
shift register empty
8
LSB
LSB
RDR read
SAM3N
SAM3N
437
437
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