M55800A Atmel Corporation, M55800A Datasheet - Page 102
M55800A
Manufacturer Part Number
M55800A
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.M55800A.pdf
(29 pages)
4.M55800A.pdf
(256 pages)
5.M55800A.pdf
(28 pages)
Specifications of M55800A
Flash (kbytes)
0 Kbytes
Pin Count
176
Max. Operating Frequency
33 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
58
Ext Interrupts
58
Usb Speed
No
Usb Interface
No
Spi
1
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
72
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3/5.0
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
Synchronous Receiver
Receiver Ready
Parity Error
Framing Error
Time-out
102
AT91X40 Series
When configured for synchronous operation (SYNC = 1), the receiver samples the RXD
signal on each rising edge of the Baud Rate clock. If a low level is detected, it is consid-
ered as a start. Data bits, parity bit and stop bit are sampled and the receiver waits for
the next start bit. See example in Figure 40.
Figure 40. Synchronous Mode: Character Reception
When a complete character is received, it is transferred to the US_RHR and the RXRDY
status bit in US_CSR is set. If US_RHR has not been read since the last transfer, the
OVRE status bit in US_CSR is set.
Each time a character is received, the receiver calculates the parity of the received data
bits, in accordance with the field PAR in US_MR. It then compares the result with the
received parity bit. If different, the parity error bit PARE in US_CSR is set.
If a character is received with a stop bit at low level and with at least one data bit at high
level, a framing error is generated. This sets FRAME in US_CSR.
This function allows an idle condition on the RXD line to be detected. The maximum
delay for which the USART should wait for a new character to arrive while the RXD line
is inactive (high level) is programmed in US_RTOR (Receiver Time-out). When this reg-
ister is set to 0, no time-out is detected. Otherwise, the receiver waits for a first character
and then initializes a counter which is decremented at each bit period and reloaded at
each byte reception. When the counter reaches 0, the TIMEOUT bit in US_CSR is set.
The user can restart the wait for a first character with the STTTO (Start Time-out) bit in
US_CR.
Calculation of time-out duration:
Example: 8-bit, parity enabled 1 stop
Sampling
SCK
RXD
True Start Detection
D0
Duration
D1
= Value x
D2
D3
4
D4
x
Bit period
D5
D6
D7
1354D–ATARM–08/02
Parity Bit
Stop Bit