M42800A Atmel Corporation, M42800A Datasheet - Page 78
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M42800A
Manufacturer Part Number
M42800A
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.M42800A.pdf
(224 pages)
4.M42800A.pdf
(27 pages)
Specifications of M42800A
Flash (kbytes)
0 Kbytes
Pin Count
144
Max. Operating Frequency
33 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
54
Usb Speed
No
Usb Interface
No
Spi
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3/5.0
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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PIO User Interface
PIO Base Address: 0xFFFF0000 (Code Label PIO_BASE)
Table 11. PIO Controller Memory Map
Notes:
78
Offset
0x0C
0x1C
0x2C
0x3C
0x4C
0x00
0x04
0x08
0x10
0x14
0x18
0x20
0x24
0x28
0x30
0x34
0x38
0x40
0x44
0x48
1. The reset value of this register depends on the level of the external pins at reset.
2. This register is cleared at reset. However, the first read of the register can give a value not equal to zero if any changes have
3. This register exists in the AT91R40008 but its value has no meaning, since the filters are not implemented.
AT91X40 Series
occurred on any pins between the reset and the read.
Register
PIO Enable Register
PIO Disable Register
PIO Status Register
Reserved
Output Enable Register
Output Disable Register
Output Status Register
Reserved
Input Filter Enable Register
Input Filter Disable Register
Input Filter Status Register
Reserved
Set Output Data Register
Clear Output Data Register
Output Data Status Register
Pin Data Status Register
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
Interrupt Status Register
(3)
PIO_SODR
PIO_CODR
PIO_ODSR
PIO_PDSR
PIO_IFDR
PIO_ODR
PIO_IFER
PIO_IFSR
PIO_PER
PIO_PDR
PIO_PSR
PIO_OER
PIO_OSR
PIO_IMR
PIO_IER
PIO_IDR
PIO_ISR
Name
–
–
–
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Write Only
Write Only
Write Only
Write Only
Write Only
Write Only
Write Only
Write Only
Write Only
Write Only
Access
–
–
–
(see also Table
1354D–ATARM–08/02
0x01FFFFFF
Reset State
(see Note 1)
(see Note 2)
10)
–
–
–
–
–
0
–
–
–
0
–
–
–
0
–
–
0
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