ATxmega64A3 Atmel Corporation, ATxmega64A3 Datasheet - Page 7

• Manufacturer Part Number: ATxmega64A3
• Manufacturer: Atmel Corporation

Specifications of ATxmega64A3

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

6. AVR CPU
6.1
6.2
8068T–AVR–12/10
Features
Overview
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The XMEGA A3 uses an 8/16-bit AVR CPU. The main function of the AVR CPU is to ensure cor-
rect program execution. The CPU must therefore be able to access memories, perform
calculations and control peripherals. Interrupt handling is described in a separate section.
6-1 on page 7
Figure 6-1.
The AVR uses a Harvard architecture - with separate memories and buses for program and
data. Instructions in the program memory are executed with a single level pipeline. While one
instruction is being executed, the next instruction is pre-fetched from the program memory.
8/16-bit high performance AVR RISC Architecture
32x8-bit registers directly connected to the ALU
Stack in RAM
Stack Pointer accessible in I/O memory space
Direct addressing of up to 16M bytes of program and data memory
True 16/24-bit access to 16/24-bit I/O registers
Support for 8-, 16- and 32-bit Arithmetic
Configuration Change Protection of system critical features
– 138 instructions
– Hardware multiplier
Peripheral
Module 1
shows the CPU block diagram.
CPU block diagram
CONTROL
STATUS/
Program
Counter
OCD
Peripheral
Module 2
Instruction
Instruction
Program
Register
Memory
Decode
Flash
DATA BUS
SRAM
DATA BUS
ALU
EEPROM
32 x 8 General
Registers
Purpose
Multiplier/
DES
PMIC
XMEGA A3
Figure
7