ATxmega256A3B Atmel Corporation, ATxmega256A3B Datasheet - Page 369

• Manufacturer Part Number: ATxmega256A3B
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3B

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Speed: No
• Usb Interface: No
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

30.11.2
8077H–AVR–12/09
NVM Flash Commands
Figure 30-2. Flash addressing for self-programming
The NVM commands that can be used for accessing the Flash Program Memory, Signature
Row and Calibration Row are listed in
For self-programming of the Flash, the Trigger for Action Triggered Commands is to set the
CMDEX bit in the NVM CTRLA register (CMDEX). The Read Triggered Commands are trig-
gered by executing the (E)LPM instruction (LPM). The Write Triggered Commands is triggered
by a executing the SPM instruction (SPM).
The Change Protected column indicate if the trigger is protected by the Configuration Change
Protection (CCP). This is a special sequence to write/execute the trigger during self-program-
ming, for more details refer to
CCP is not required for external programming. The two last columns shows the address pointer
used for addressing, and the source/destination data register.
Section 30.11.1.1 on page 367
algorithm for each NVM operation.
FLASHEND
FPAGE
00
01
02
PROGRAM MEMORY
Z-Pointer
BIT
PAGE
WITHIN THE FLASH
PAGEMSB
PAGE ADDRESS
”CCP - Configuration Change Protection Register” on page
through
FPAGE
Table
Section 30.11.2.14 on page 374
30-2.
WORDMSB
FWORD
WORD ADDRESS
WITHIN A PAGE
INSTRUCTION WORD
1
0/1
0
PAGE
Low/High Byte select for (E)LPM
explain in details the
XMEGA A
00
01
02
PAGEEND
FWORD
369
13.