ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 58

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

5.14.2
5.14.3
8291A–AVR–10/11
CTRLB – Control Register B
ADDRCTRL – Address Control Register
• Bit 7 – CHBUSY - Busy
When the DMA channel starts a DMA transaction, the CHBUSY flag will be read as one. This
flag is automatically cleared when the DMA channel is disabled, when the channel transaction
complete interrupt flag is set or when the channel error interrupt flag is set.
• Bit 6 – CHPEND - Pending
If a block transfer is pending on the DMA channel, the CHPEND flag will be read as one. This
flag is automatically cleared when the transfer starts or if the transfer is aborted.
• Bit 5 – ERRIF - Error Interrupt Flag
If an error condition is detected on the DMA channel, the ERRIF flag will be set and the optional
interrupt is generated. Since the DMA channel error interrupt shares the interrupt address with
the DMA channel n transaction complete interrupt, ERRIF will not be cleared when the interrupt
vector is executed. This flag is cleared by writing a one to this location.
• Bit 4 – TRNIF - Transaction Complete Interrupt Flag
When a transaction on the DMA channel has been completed, the TRNIF flag will be set and the
optional interrupt is generated. When repeat is not enabled, the transaction is complete and
TRNIFR is set after the block transfer. When unlimited repeat is enabled, TRNIF is also set after
each block transfer.
Since the DMA channel transaction n complete interrupt shares the interrupt address with the
DMA channel error interrupt, TRNIF will not be cleared when the interrupt vector is executed.
This flag is cleared by writing a one to this location.
• Bit 3:2 – ERRINTLVL[1:0]: Error Interrupt Level
These bits enable the interrupt for DMA channel transfer errors and select the interrupt level, as
described in
enabled interrupt will trigger for the conditions when ERRIF is set.
• Bit 1:0 – TRNINTLVL[1:0]: Transaction Complete Interrupt Level
These bits enable the interrupt for DMA channel transaction completes and select the interrupt
level, as described in
The enabled interrupt will trigger for the conditions when TRNIF is set.
Bit
+0x02
Read/Write
Initial Value
Bit
+0x04
Read/Write
Initial Value
CHBUSY
”Interrupts and Programmable Multilevel Interrupt Controller” on page
R/W
SRCRELOAD[1:0]
7
0
R
7
0
”Interrupts and Programmable Multilevel Interrupt Controller” on page
CHPEND
R/W
6
0
6
R
0
ERRIF
R/W
R/W
5
0
5
0
SRCDIR[1:0]
TRNIF
R/W
R/W
4
0
4
0
DESTRELOAD[1:0]
R/W
3
R
0
ERRINTLVL[1:0]
3
0
Atmel AVR XMEGA B
R/W
R/W
2
0
2
0
R/W
R/W
1
0
DESTDIR[1:0]
1
TRNINTLVL[1:0]
0
R/W
R/W
0
0
0
0
119. The
ADDRCTRL
CTRLB
119.
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