ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 49

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

26. AES and DES Crypto Engine
26.1
26.2
8330B–AVR–10/11
Features
Overview
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The Advanced Encryption Standard (AES) and Data Encryption Standard (DES) are two com-
monly used standards for cryptography. These are supported through an AES peripheral
module and a DES CPU instruction, and the communication interfaces and the CPU can use
these for fast, encrypted communication and secure data storage.
DES is supported by an instruction in the AVR CPU. The 8-byte key and 8-byte data blocks must
be loaded into the register file, and then the DES instruction must be executed 16 times to
encrypt/decrypt the data block.
The AES crypto module encrypts and decrypts 128-bit data blocks with the use of a 128-bit key.
The key and data must be loaded into the key and state memory in the module before encryp-
tion/decryption is started. It takes 375 peripheral clock cycles before the encryption/decryption is
done. The encrypted/encrypted data can then be read out, and an optional interrupt can be gen-
erated. The AES crypto module also has DMA support with transfer triggers when
encryption/decryption is done and optional auto-start of encryption/decryption when the state
memory is fully loaded.
Data Encryption Standard (DES) CPU instruction
Advanced Encryption Standard (AES) crypto module
DES Instruction
AES crypto module
– Encryption and decryption
– DES supported
– Encryption/decryption in 16 CPU clock cycles per 8-byte block
– Encryption and decryption
– Supports 128-bit keys
– Supports XOR data load mode to the state memory
– Encryption/decryption in 375 clock cycles per 16-byte block
XMEGA B1
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