ATUC64D3 Atmel Corporation, ATUC64D3 Datasheet - Page 55

• Manufacturer Part Number: ATUC64D3
• Manufacturer: Atmel Corporation

Specifications of ATUC64D3

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 48 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 25
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 51
• Ext Interrupts: 51
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

6.2.2.2
6.2.2.3
6.2.2.4
6.2.2.5
6.3
32000D–04/2011
Example of MPU functionality
TLB Multiple Hit Violation
DTLB Protection Violation
ITLB Miss Violation
DTLB Miss Violation
An DTLB protection violation is issued if a data access violates access permissions. The violat-
ing access is not executed. The address of the failing instruction is placed on the system stack.
An ITLB miss violation is issued if an instruction fetch does not hit in any region. The violating
instruction is not executed. The address of the failing instruction is placed on the system stack.
An DTLB miss violation is issued if a data access does not hit in any region. The violating access
is not executed. The address of the failing instruction is placed on the system stack.
An access hit in multiple protection regions. The address of the failing instruction is placed on
the system stack. This is a critical system error that should not occur.
As an example, consider region 0. Let region 0 be of size 16 KB, thus each subregion is 1KB.
Subregion 0 has offset 0-1KB from the base address, subregion 1 has offset 1KB-2KB and so
on.
MPUAPRA and MPUAPRB each has one field per region. Each subregion in region 0 can get its
access permissions from either MPUAPRA[AP0] or MPUAPRB[AP0], this is selected by the sub-
region’s bitfield in MPUPSR0.
Let:
MPUPSR0 = {0b0000_0000_0000_0000, 0b1010_0000_1111_0101}
MPUAPRA = {A, B, C, D, E, F, G, H}
MPUAPRB = {a, b, c, d, e, f, g, h}
where {A-H, a-h} have legal values as defined in
Thus for region 0:
Table 6-4.
Subregion
0
1
2
3
4
5
6
7
Example of access rights for subregions
Access
permission
h
H
h
H
h
h
h
h
Subregion
8
9
10
11
12
13
14
15
Access
permission
H
H
H
H
H
h
H
h
Table
6-3.
AVR32
55