ATUC128D3 Atmel Corporation, ATUC128D3 Datasheet - Page 37
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ATUC128D3
Manufacturer Part Number
ATUC128D3
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.ATUC128D3.pdf
(755 pages)
5.ATUC128D3.pdf
(69 pages)
Specifications of ATUC128D3
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
48 MHz
Cpu
32-bit AVR
# Of Touch Channels
25
Hardware Qtouch Acquisition
Yes
Max I/o Pins
51
Ext Interrupts
51
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
7
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- ATUC128D3 PDF datasheet #4
- ATUC128D3 PDF datasheet #5
- Current page: 37 of 377
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5.2
32000D–04/2011
Understanding the MMU
Figure 5-2.
The AVR32 Memory Management Unit (MMU) is responsible for mapping virtual to physical
addresses. When a memory access is performed, the MMU translates the virtual address speci-
fied into a physical address, while checking the access permissions. If an error occurs in the
translation process, or Operating System intervention is needed for some reason, the MMU will
issue an exception, allowing the problem to be resolved by software.
The MMU architecture uses paging to map memory pages from the 32-bit virtual address space
to a 32-bit physical address space. Page sizes of 1, 4, 64 kilobytes and 1 megabyte are sup-
ported. Each page has individual access rights, providing fine protection granularity.
The information needed in order to perform the virtual-to-physical mapping resides in a page
table. Each page has its own entry in the page table. The page table also contains protection
information and other data needed in the translation process. Conceptually, the page table is
accessed for every memory access, in order to read the mapping information for each page.
In order to speed up the translation process, a special page table cache is used. This cache is
called a Translation Lookaside Buffer (TLB). The TLB contains the n most recently used page
table entries. The number n of entries in the TLB is IMPLEMENTATION DEFINED. It is also
IMPLEMENTATION DEFINED whether a single unified TLB should be used for both instruction
and memory accesses, or if two separate TLBs are implemented. The architecture supports one
or two TLBs with up to 64 entries in each. TLB entries can also be locked in the TLB, guarantee-
ing high-speed memory accesses.
0xFFFFFFFF
0xC0000000
0xE0000000
0xA0000000
0x80000000
0x00000000
P0 / U0
P4
P3
P2
P1
The AVR32 segment translation map
512MB translated space,
512MB system space,
512MB non-translated
512MB non-translated
space, non-cacheable
Virtual address space
2GB translated space
space, cacheable
non-cacheable
cacheable
cacheable
translation
Segment
Physical address space
512MB physical address
2GB physical address
space
space
0xFFFFFFFF
0xE0000000
0x80000000
0x20000000
0x00000000
AVR32
37
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