ATtiny9 Atmel Corporation, ATtiny9 Datasheet
ATtiny9
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ATtiny9 Summary of contents
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Features • High Performance, Low Power AVR • Advanced RISC Architecture – 54 Powerful Instructions – Most Single Clock Cycle Execution – General Purpose Working Registers – Fully Static Operation – MIPS Throughput at ...
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Pin Configurations Figure 1-1. (PCINT1/TPICLK/CLKI/ICP0/OC0B/ADC1/AIN1) PB1 (PCINT1/TPICLK/CLKI/ICP0/OC0B/ADC1/AIN1) PB1 1.1 Pin Description 1.1.1 VCC Supply voltage. 1.1.2 GND Ground. 1.1.3 Port B (PB3..PB0) This is a 4-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit. The ...
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Overview ATtiny4/5/9/10 are low-power CMOS 8-bit microcontrollers based on the compact AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny4/5/9/10 achieve throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize ...
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... Flash allows program memory to be re-programmed in-system by a conventional, non-volatile memory programmer. The ATtiny4/5/9/10 AVR are supported by a suite of program and system development tools, including macro assemblers and evaluation kits. 2.1 Comparison of ATtiny4, ATtiny5, ATtiny9 and ATtiny10 A comparison of the devices is shown in Table 2-1. ATtiny4/5/9/10 4 ...
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General Information 3.1 Resources A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for download at http://www.atmel.com/avr. 3.2 Code Examples This documentation contains simple code examples that briefly show how to use ...
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Register Summary Address Name Bit 7 0x3F SREG I 0x3E SPH 0x3D SPL 0x3C CCP 0x3B RSTFLR – 0x3A SMCR – 0x39 OSCCAL 0x38 Reserved – 0x37 CLKMSR – 0x36 CLKPSR – 0x35 PRR – 0x34 VLMCSR VLMF 0x33 ...
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Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI ...
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Instruction Set Summary Mnemonics Operands ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add without Carry ADC Rd, Rr Add with Carry SUB Rd, Rr Subtract without Carry SUBI Rd, K Subtract Immediate SBC Rd, Rr Subtract with Carry SBCI ...
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Mnemonics Operands BCLR s Flag Clear SBI A, b Set Bit in I/O Register CBI A, b Clear Bit in I/O Register BST Rr, b Bit Store from Register to T BLD Rd, b Bit load from T to Register ...
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Ordering Information 6.1 ATtiny4 Supply Voltage Speed 12 MHz 1.8 – 5.5V 10 MHz Notes: 1. For speed vs. supply voltage, see section 2. All packages are Pb-free, halide-free and fully green and they comply with the European directive ...
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ATtiny5 Supply Voltage Speed 12 MHz 1.8 – 5.5V 10 MHz Notes: 1. For speed vs. supply voltage, see section 2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of ...
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... Plastic Ultra Thin Dual Flat No Lead (UDFN) ATtiny4/5/9/10 12 (1) Temperature Industrial (4) (-40°C to 85°C) Extended (7) (-40°C to 125°C) 16.3 “Speed” on page 118. Package Type (2) (3) Package Ordering Code (5) 6ST1 ATtiny9-TSHR (6) 8MA4 ATtiny9-MAHR (5) 6ST1 ATtiny9-TS8R 8127ES–AVR–11/11 ...
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ATtiny10 Supply Voltage Speed 12 MHz 1.8 – 5.5V 10 MHz Notes: 1. For speed vs. supply voltage, see section 2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of ...
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Packaging Information 7.1 6ST1 Pin # Top View 0. View B Notes: 1. This package is compliant with JEDEC specification MO-178 Variation AB 2. Dimension D does ...
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E Pin TOP VIEW C0.2 4 BOTTOM VIEW Note: 1. ALL DIMENSIONS ARE IN mm. ANGLES IN DEGREES. 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL ...
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Errata The revision letters in this section refer to the revision of the corresponding ATtiny4/5/9/10 device. 8.1 ATtiny4 8.1.1 Rev. E • Programming Lock Bits 1. Programming Lock Bits Programming Lock Bits to a lock mode equal or lower ...
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... Problem Fix / Workaround When programming Lock Bits, make sure lock mode is not set to present, or lower levels. 8.2.3 Rev. A – C Not sampled. 8.3 ATtiny9 8.3.1 Rev. E • Programming Lock Bits 1. Programming Lock Bits Programming Lock Bits to a lock mode equal or lower than the current causes one word of Flash to be corrupted ...
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Rev. A – C Not sampled. 8.4 ATtiny10 8.4.1 Rev. E • Programming Lock Bits 1. Programming Lock Bits Programming Lock Bits to a lock mode equal or lower than the current causes one word of Flash to be ...
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... Added topside and bottomside marking notes in page 5. Added ESD errata, see 6. Added Lock bits re-programming errata, see 9.4 Rev. 8127B – 08/09 1. Updated document template 2. Expanded document to also cover devices ATtiny4, ATtiny5 and ATtiny9 3. Added section: – 4. Updated sections: – – – – ...
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... Words and Pages in the Flash (ATtiny4/5)” on page 110 “Active Clock Domains and Wake-up Sources in Different Sleep Modes” on page 23 “Reset and Interrupt Vectors” on page 36 “Number of Words and Pages in the Flash (ATtiny9/10)” on page 110 “Signature codes” on page 111 8127ES–AVR–11/11 ...
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ATtiny4/5/9/10 21 ...
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