ATtiny4 Atmel Corporation, ATtiny4 Datasheet - Page 95

• Manufacturer Part Number: ATtiny4
• Manufacturer: Atmel Corporation

Specifications of ATtiny4

• Flash (kbytes): 0.5 Kbytes
• Pin Count: 6
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 1
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 4
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.03
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 2
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

13.12.3
8127E–AVR–11/11
ADCSRB
–
ADC Control and Status Register B
• Bit 4 – ADIF: ADC Interrupt Flag
This bit is set when an ADC conversion completes and the data registers are updated. The ADC
Conversion Complete Interrupt is requested if the ADIE bit is set. ADIF is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by
writing a logical one to the flag.
• Bit 3 – ADIE: ADC Interrupt Enable
When this bit is written to one, the ADC Conversion Complete Interrupt request is enabled.
• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits
These bits determine the division factor between the system clock frequency and the input clock
to the ADC.
Table 13-3.
• Bits 7:3 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bits 2:0 – ADTS2:0: ADC Auto Trigger Source
If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger
an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion
will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a trig-
ger source that is cleared to a trigger source that is set, will generate a positive edge on the
Bit
0x1C
Read/Write
Initial Value
ADPS2
0
0
0
0
1
1
1
1
ADC Prescaler Selections
R
7
–
0
R
6
–
0
ADPS1
0
0
1
1
0
0
1
1
R
5
–
0
R
4
–
0
ADPS0
0
1
0
1
0
1
0
1
R
3
–
0
ADTS2
R/W
2
0
ADTS1
R/W
1
0
ATtiny4/5/9/10
Division Factor
ADTS0
R/W
0
0
128
16
32
64
2
2
4
8
ADCSRB
95