ATtiny24 Automotive Atmel Corporation, ATtiny24 Automotive Datasheet - Page 122
![no-image](/images/manufacturer_photos/0/0/79/atmel_corporation_sml.jpg)
ATtiny24 Automotive
Manufacturer Part Number
ATtiny24 Automotive
Description
Manufacturer
Atmel Corporation
Specifications of ATtiny24 Automotive
Flash (kbytes)
2 Kbytes
Pin Count
14
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
4
Hardware Qtouch Acquisition
No
Max I/o Pins
12
Ext Interrupts
12
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.12
Eeprom (bytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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16. USI – Universal Serial Interface
16.1
16.2
122
Features
Overview
Atmel ATtiny24/44/84 [Preliminary]
•
•
•
•
•
•
The universal serial interface (USI) provides the basic hardware resources needed for serial
communication. Combined with a minimum of control software, the USI allows significantly
higher transfer rates and uses less code space than solutions based on software only. Inter-
rupts are included to minimize the processor load.
A simplified block diagram of the USI is shown in
placement of I/O pins, refer to
Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register
and bit locations are listed in the
Figure 16-1. Universal Serial Interface, Block Diagram
The 8-bit shift register is directly accessible via the data bus and contains the incoming and
outgoing data. The register has no buffering, so the data must be read as quickly as possible
to ensure that no data are lost. The most significant bit is connected to one of two output pins,
depending on the wire mode configuration. A transparent latch is inserted between the serial
register output and output pin, which delays the change of data output to the opposite clock
edge of the data input sampling. The serial input is always sampled from the data input (DI)
pin independent of the configuration.
Two-wire Synchronous Data Transfer (Master or Slave)
Three-wire Synchronous Data Transfer (Master or Slave)
Data Received Interrupt
Wakeup from Idle Mode
In Two-wire Mode: Wakeup from All Sleep Modes, Including Power-down Mode
Two-wire Start Condition Detector with Interrupt Capability
USIDR
USISR
USICR
2
4-bit Counter
“Pinout Atmel
“Register Descriptions” on page
3
2
1
0
3
2
1
0
D Q
LE
®
[1]
ATtiny24/44/84” on page
TIM0 COMP
0
1
Figure 16-1 on page
Two-wire Clock
Control Unit
130.
CLOCK
HOLD
2. CPU accessible I/O
122. For the actual
DO
DI/SDA
USCK/SCL
7701E–AVR–02/11
(Output only)
(Input/Open Drain)
(Input/Open Drain)
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