ATtiny2313 Atmel Corporation, ATtiny2313 Datasheet - Page 78

• Manufacturer Part Number: ATtiny2313
• Manufacturer: Atmel Corporation

Specifications of ATtiny2313

• Flash (kbytes): 2 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 4
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 18
• Ext Interrupts: 18
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

Timer/Counter
Interrupt Mask
Register – TIMSK
Timer/Counter
Interrupt Flag Register
– TIFR
78
ATtiny2313
• Bit 4 – Res: Reserved Bit
This bit is reserved bit in the ATtiny2313 and will always read as zero.
• Bit 2 – OCIE0B: Timer/Counter0 Output Compare Match B Interrupt Enable
When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if
a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the Timer/Counter
Interrupt Flag Register – TIFR.
• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter 0 Inter-
rupt Flag Register – TIFR.
• Bit 0 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed
if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the
Timer/Counter 0 Interrupt Flag Register – TIFR.
• Bit 4 – Res: Reserved Bit
This bit is reserved bit in the ATtiny2313 and will always read as zero.
• Bit 2 – OCF0B: Output Compare Flag 0 B
The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in
OCR0B – Output Compare Register0 B. OCF0B is cleared by hardware when executing the cor-
responding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to
the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable),
and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed.
• Bit 1 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by
writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt
Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed.
The setting of this flag is dependent of the WGM02:0 bit setting. Refer to
Generation Mode Bit Description” on page
• Bit 0 – OCF0A: Output Compare Flag 0 A
The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data
in OCR0A – Output Compare Register0 A. OCF0A is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
TOIE1
TOV1
R/W
R/W
7
0
7
0
OCIE1A
OCF1A
R/W
R/W
6
0
6
0
OCF1B
OCIE1B
R/W
R/W
5
0
5
0
R
0
4
–
R
4
–
0
75.
ICF1
R/W
ICIE1
R/W
3
0
3
0
OCF0B
OCIE0B
R/W
R/W
2
0
2
0
TOV0
R/W
TOIE0
1
0
R/W
1
0
OCF0A
OCIE0A
R/W
0
0
R/W
Table
0
0
40,
TIFR
TIMSK
2543L–AVR–08/10
“Waveform