ATtiny20 Atmel Corporation, ATtiny20 Datasheet - Page 57
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ATtiny20
Manufacturer Part Number
ATtiny20
Description
Manufacturer
Atmel Corporation
Specifications of ATtiny20
Flash (kbytes)
2 Kbytes
Pin Count
14
Max. Operating Frequency
12 MHz
Cpu
8-bit AVR
# Of Touch Channels
5
Hardware Qtouch Acquisition
Yes
Max I/o Pins
12
Ext Interrupts
12
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.12
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
3
32khz Rtc
No
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATtiny20-MMHR
Manufacturer:
ATMEL
Quantity:
20 000
Part Number:
ATtiny20-SSU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATtiny20-XU
Manufacturer:
Atmel
Quantity:
904
8235B–AVR–04/11
Table 10-8 on page 57
overriding signals shown in
Table 10-8.
1.
2.
Table 10-9.
1.
Note:
Signal
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
Signal
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
RSTDISBL is 1 when the configuration bit is “0” (programmed)
CKOUT is 1 when the configuration bit is “0” (programmed)
EXT_CLOCK = external clock is selected as system clock.
When TWI is enabled the slew rate control and spike filter are activate on PB1. This is not illus-
trated in
TWEN • SPE • MSTR • SPI_MASTER_OUT +
RSTDISBL
RSTDISBL
TWEN + (SPE • MSTR) + OC1A_ENABLE
Overriding Signals for Alternate Functions in PB[3:2]
Overriding Signals for Alternate Functions in PB[1:0]
Figure 10-6 on page
PB3/
TWEN • (SPE + MSTR) • OC1A
PB1/OC1A/SDA/MOSI/PCINT9
PCINT11 Input
PCINT9 / SPI Slave Input
RESET/
RSTDISBL
(SPE • MSTR) + TWEN
RSTDISBL
RSTDISBL
(1)
(1)
and
TWEN • SDA_OUT
+ (PCINT11 • PCIE1)
PCINT9 • PCIE1
PCINT9 • PCIE1
• PCINT11 • PCIE1
1
0
0
0
Figure 10-6 on page
Table 10-9 on page 57
SDA Input
PCINT11
(1)
(1)
(1)
0
0
0
50. The spike filter is connected between AIOxn and the TWI.
CKOUT
OC1B_ENABLE • OC1B + CKOUT • (SPE + MSTR)
50.
PB2/INT0/OC0A/OC1B/MISO/CKOUT/PCINT10
CKOUT + OC0A_ENABLE + OC1B_ENABLE +
SPI_SLAVE_OUT + CKOUT • (SPE + MSTR) •
relate the alternate functions of Port B to the
(2)
INT0 / PCINT10 / SPI Master Input
• System Clock + CKOUT • SPE • MSTR •
(PCINT10 • PCIE1) + INT0
CKOUT
(PCINT10 • PCIE1) + INT0
• OC1B_ENABLE • OC0A
EXT_CLOCK
( EXT_CLOCK
(EXT_CLOCK
CLOCK / PCINT8 / T0 Input
(SPE • MSTR)
PB0/T0/CLKI/PCINT8
(2)
CKOUT
CKOUT
+ (SPE • MSTR)
EXT_CLOCK
EXT_CLOCK
EXT_CLOCK
0
0
(1)
(1)
(1)
(2)
(2)
+ (PCINT8 • PCIE1)
• PCINT8 • PCIE1)
0
0
0
0
• PWR_DOWN ) +
ATtiny20
(1)
(1)
(1)
57