ATmega8A Atmel Corporation, ATmega8A Datasheet - Page 14

• Manufacturer Part Number: ATmega8A
• Manufacturer: Atmel Corporation

Specifications of ATmega8A

• Flash (kbytes): 8 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 23
• Ext Interrupts: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Pwm Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

6.7.1
8159D–AVR–02/11
Interrupt Response Time
CLI instruction. The following example shows how this can be used to avoid interrupts during the
timed EEPROM write sequence.
When using the SEI instruction to enable interrupts, the instruction following SEI will be exe-
cuted before any pending interrupts, as shown in the following example.
The interrupt execution response for all the enabled Atmel
minimum. After four clock cycles, the Program Vector address for the actual interrupt handling
routine is executed. During this 4-clock cycle period, the Program Counter is pushed onto the
Stack. The Vector is normally a jump to the interrupt routine, and this jump takes three clock
cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is com-
pleted before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the
interrupt execution response time is increased by four clock cycles. This increase comes in addi-
tion to the start-up time from the selected sleep mode.
A return from an interrupt handling routine takes four clock cycles. During these four clock
cycles, the Program Counter (2 bytes) is popped back from the Stack, the Stack Pointer is incre-
mented by 2, and the I-bit in SREG is set.
Assembly Code Example
C Code Example
Assembly Code Example
C Code Example
in r16, SREG
cli
sbi EECR, EEMWE
sbi EECR, EEWE
out SREG, r16
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1<<EEMWE); /* start EEPROM write */
EECR |= (1<<EEWE);
SREG = cSREG; /* restore SREG value (I-bit) */
sei
sleep; enter sleep, waiting for interrupt
; note: will enter sleep before any pending
; interrupt(s)
_SEI(); /* set global interrupt enable */
_SLEEP(); /* enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s) */
; set global interrupt enable
; disable interrupts during timed sequence
; store SREG value
; start EEPROM write
; restore SREG value (I-bit)
®
AVR
®
interrupts is four clock cycles
ATmega8A
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