ATmega88 Automotive Atmel Corporation, ATmega88 Automotive Datasheet - Page 175
ATmega88 Automotive
Manufacturer Part Number
ATmega88 Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.ATMEGA168_AUTOMOTIVE.pdf
(19 pages)
3.ATMEGA168_AUTOMOTIVE.pdf
(340 pages)
4.ATMEGA88_AUTOMOTIVE.pdf
(10 pages)
Specifications of ATmega88 Automotive
Flash (kbytes)
8 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
23
Ext Interrupts
24
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 150
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
- AT90CAN128_AUTOMOTIVE PDF datasheet
- ATMEGA168_AUTOMOTIVE PDF datasheet #2
- ATMEGA168_AUTOMOTIVE PDF datasheet #3
- ATMEGA88_AUTOMOTIVE PDF datasheet #4
- Current page: 175 of 340
- Download datasheet (6Mb)
17.5.3
17.5.4
17.5.5
17.6
7530I–AVR–02/10
Data Reception – The USART Receiver
Transmitter Flags and Interrupts
Parity Generator
Disabling the Transmitter
The USART Transmitter has two flags that indicate its state: USART Data Register Empty
(UDREn) and Transmit Complete (TXCn). Both flags can be used for generating interrupts.
The Data Register Empty (UDREn) Flag indicates whether the transmit buffer is ready to receive
new data. This bit is set when the transmit buffer is empty, and cleared when the transmit buffer
contains data to be transmitted that has not yet been moved into the Shift Register. For compat-
ibility with future devices, always write this bit to zero when writing the UCSRnA Register.
When the Data Register Empty Interrupt Enable (UDRIEn) bit in UCSRnB is written to one, the
USART Data Register Empty Interrupt will be executed as long as UDREn is set (provided that
global interrupts are enabled). UDREn is cleared by writing UDRn. When interrupt-driven data
transmission is used, the Data Register Empty interrupt routine must either write new data to
UDRn in order to clear UDREn or disable the Data Register Empty interrupt, otherwise a new
interrupt will occur once the interrupt routine terminates.
The Transmit Complete (TXCn) Flag bit is set one when the entire frame in the Transmit Shift
Register has been shifted out and there are no new data currently present in the transmit buffer.
The TXCn Flag bit is automatically cleared when a transmit complete interrupt is executed, or it
can be cleared by writing a one to its bit location. The TXCn Flag is useful in half-duplex commu-
nication interfaces (like the RS-485 standard), where a transmitting application must enter
receive mode and free the communication bus immediately after completing the transmission.
When the Transmit Compete Interrupt Enable (TXCIEn) bit in UCSRnB is set, the USART
Transmit Complete Interrupt will be executed when the TXCn Flag becomes set (provided that
global interrupts are enabled). When the transmit complete interrupt is used, the interrupt han-
dling routine does not have to clear the TXCn Flag, this is done automatically when the interrupt
is executed.
The Parity Generator calculates the parity bit for the serial frame data. When parity bit is enabled
(UPMn1 = 1), the transmitter control logic inserts the parity bit between the last data bit and the
first stop bit of the frame that is sent.
The disabling of the Transmitter (setting the TXEN to zero) will not become effective until ongo-
ing and pending transmissions are completed, i.e., when the Transmit Shift Register and
Transmit Buffer Register do not contain data to be transmitted. When disabled, the Transmitter
will no longer override the TxDn pin.
The USART Receiver is enabled by writing the Receive Enable (RXENn) bit in the
UCSRnB Register to one. When the Receiver is enabled, the normal pin operation of the RxDn
pin is overridden by the USART and given the function as the Receiver’s serial input. The baud
rate, mode of operation and frame format must be set up once before any serial reception can
be done. If synchronous operation is used, the clock on the XCKn pin will be used as transfer
clock.
ATmega48/88/168 Automotive
175
Related parts for ATmega88 Automotive
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
IC MCU AVR 8K 5V 20MHZ 32-TQFP
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
MCU AVR 8K FLASH 15MHZ 32-QFN
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
IC AVR MCU 8K 20MHZ 5V 32TQFP
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
IC AVR MCU 8K 20MHZ 5V 32-QFN
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
IC AVR MCU 8K 20MHZ 5V 28DIP
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
Manufacturer:
Atmel Corporation
Datasheet:
Part Number:
Description:
IC MCU AVR 8K 5V 20MHZ 32-TQFP
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
IC MCU AVR 8K 5V 20MHZ 32-QFN
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
IC MCU AVR 8K 5V 20MHZ 32-QFN
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
IC MCU AVR 8K 5V 20MHZ 28-DIP
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
IC MCU AVR 8K 5V 20MHZ 28-DIP
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
MCU AVR 8K FLASH 20MHZ 32TQFP
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
MCU AVR 8K FLASH 20MHZ 32QFN
Manufacturer:
Atmel
Datasheet: