ATmega64M1 Automotive Atmel Corporation, ATmega64M1 Automotive Datasheet - Page 35
ATmega64M1 Automotive
Manufacturer Part Number
ATmega64M1 Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.ATMEGA16M1_AUTOMOTIVE.pdf
(25 pages)
3.ATMEGA16M1_AUTOMOTIVE.pdf
(367 pages)
Specifications of ATmega64M1 Automotive
Flash (kbytes)
64 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
27
Ext Interrupts
27
Usb Speed
No
Usb Interface
No
Spi
1
Uart
1
Can
1
Lin
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 150
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
14
Input Capture Channels
1
Pwm Channels
10
32khz Rtc
No
Calibrated Rc Oscillator
Yes
- AT90CAN128_AUTOMOTIVE PDF datasheet
- ATMEGA16M1_AUTOMOTIVE PDF datasheet #2
- ATMEGA16M1_AUTOMOTIVE PDF datasheet #3
- Current page: 35 of 367
- Download datasheet (7Mb)
Figure 5-3.
7647G–AVR–09/11
XTAL1
XTAL2
RC OSCILLATOR
OSCCAL
8 MHz
PLL Clocking System
OSCILLATORS
Table 5-7.
1.
2.
3.
RC Osc
Ext Osc
CKSEL
Ext Clk
0011
0101
0001
3..0
CKSEL3..0
This value do not provide a proper restart ; do not use PD in this clock scheme
This value do not provide a proper restart ; do not use PD in this clock scheme
This value do not provide a proper restart ; do not use PD in this clock scheme
SUT1..0
Start-up Times when the PLL is selected as system clock
00
01
10
11
00
01
10
11
00
01
10
11
DIVIDE
BY 8
Start-up Time from Power-down
and Power-save
PLLE
PLL
64x
Atmel ATmega16/32/64/M1/C1
16K CK
16K CK
16K CK
6 CK
6 CK
6 CK
1K CK
1K CK
1K CK
1K CK
1K CK
(1)
(2)
(3)
Detector
Lock
DIVIDE
DIVIDE
PLLF
BY 2
BY 4
Reserved
Additional Delay from Reset
14CK + 64 ms
14CK + 64 ms
14CK + 64 ms
14CK + 4 ms
14CK + 4 ms
14CK + 4 ms
14CK + 4 ms
(V
CC
14CK
14CK
14CK
14CK
= 5.0V)
CLK
PLOCK
CK
PLL
SOURCE
35
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