ATmega64A Atmel Corporation, ATmega64A Datasheet - Page 87

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ATmega64A

Manufacturer Part Number
ATmega64A
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega64A

Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
53
Ext Interrupts
8
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
8
Input Capture Channels
2
Pwm Channels
7
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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13.3.7
8160C–AVR–07/09
Alternate Functions of Port G
Table 13-20. Overriding Signals for Alternate Functions in PF3:PF0
In ATmega103 compatibility mode, only the alternate functions are the defaults for Port G, and
Port G cannot be used as General Digital Port Pins. The alternate pin configuration is as follows:
Table 13-21. Port G Pins Alternate Functions
• TOSC1 – Port G, Bit 4
TOSC2, Timer Oscillator pin 1: When the AS0 bit in ASSR is set (one) to enable asynchronous
clocking of Timer/Counter0, pin PG4 is disconnected from the port, and becomes the inverting
output of the Oscillator amplifier. In this mode, a crystal Oscillator is connected to this pin, and
the pin can not be used as an I/O pin.
• TOSC2 – Port G, Bit 3
TOSC2, Timer Oscillator pin 2: When the AS0 bit in ASSR is set (one) to enable asynchronous
clocking of Timer/Counter0, pin PG3 is disconnected from the port, and becomes the input of the
inverting Oscillator amplifier. In this mode, a crystal Oscillator is connected to this pin, and the
pin cannot be used as an I/O pin.
• ALE – Port G, Bit 2
ALE is the external data memory Address Latch Enable signal.
• RD – Port G, Bit 1
RD is the external data memory read control strobe.
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Port Pin
PG4
PG3
PG2
PG1
PG0
PF3/ADC3
0
0
0
0
0
0
0
0
ADC3 INPUT
Alternate Function
TOSC1 (RTC Oscillator Timer/Counter0)
TOSC2 (RTC Oscillator Timer/Counter0)
ALE (Address Latch Enable to external memory)
RD (Read strobe to external memory)
WR (Write strobe to external memory)
PF2/ADC2
0
0
0
0
0
0
0
0
ADC2 INPUT
PF1/ADC1
0
0
0
0
0
0
0
0
ADC1 INPUT
ATmega64A
PF0/ADC0
0
0
0
0
0
0
0
0
ADC0 INPUT
87

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