ATmega48A Atmel Corporation, ATmega48A Datasheet

ATmega48A

Manufacturer Part Number

ATmega48A

Description

Manufacturer

Atmel Corporation

Datasheets

1.ATMEGA168A.pdf (567 pages)

2.ATMEGA168A.pdf (35 pages)

Specifications of ATmega48A

Flash (kbytes)

4 Kbytes

Pin Count

Max. Operating Frequency

20 MHz

Cpu

8-bit AVR

# Of Touch Channels

Hardware Qtouch Acquisition

Max I/o Pins

Ext Interrupts

Usb Speed

Usb Interface

Spi

Twi (i2c)

Uart

Graphic Lcd

Video Decoder

Camera Interface

Adc Channels

Adc Resolution (bits)

Adc Speed (ksps)

Analog Comparators

Resistive Touch Screen

Temp. Sensor

Yes

Crypto Engine

Sram (kbytes)

0.5

Eeprom (bytes)

256

Self Program Memory

Dram Memory

Nand Interface

Picopower

Temp. Range (deg C)

-40 to 85

I/o Supply Class

1.8 to 5.5

Operating Voltage (vcc)

1.8 to 5.5

Fpu

Mpu / Mmu

no / no

Timers

Output Compare Channels

Input Capture Channels

Pwm Channels

32khz Rtc

Yes

Calibrated Rc Oscillator

Yes

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Price

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Features

•

High Performance, Low Power Atmel

Advanced RISC Architecture

High Endurance Non-volatile Memory Segments

Atmel

Peripheral Features

Special Microcontroller Features

I/O and Packages

Operating Voltage:

Temperature Range:

Speed Grade:

Power Consumption at 1MHz, 1.8V, 25°C

– 131 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 20 MIPS Throughput at 20MHz

– On-chip 2-cycle Multiplier

– 4/8/16/32KBytes of In-System Self-Programmable Flash program memory

– 256/512/512/1KBytes EEPROM

– 512/1K/1K/2KBytes Internal SRAM

– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM

– Data retention: 20 years at 85°C/100 years at 25°C

– Optional Boot Code Section with Independent Lock Bits

– Programming Lock for Software Security

– Capacitive touch buttons, sliders and wheels

– QTouch and QMatrix

– Up to 64 sense channels

– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode

– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

– Real Time Counter with Separate Oscillator

– Six PWM Channels

– 8-channel 10-bit ADC in TQFP and QFN/MLF package

– 6-channel 10-bit ADC in PDIP Package

– Programmable Serial USART

– Master/Slave SPI Serial Interface

– Byte-oriented 2-wire Serial Interface (Philips I

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

– Interrupt and Wake-up on Pin Change

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated Oscillator

– External and Internal Interrupt Sources

– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby,

– 23 Programmable I/O Lines

– 28-pin PDIP, 32-lead TQFP, 28-pad QFN/MLF and 32-pad QFN/MLF

– 1.8 - 5.5V

– -40

– 0 - 4MHz@1.8 - 5.5V, 0 - 10MHz@2.7 - 5.5.V, 0 - 20MHz @ 4.5 - 5.5V

– Active Mode: 0.2mA

– Power-down Mode: 0.1µA

– Power-save Mode: 0.75µA (Including 32kHz RTC)

Mode

and Extended Standby

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

Temperature Measurement

QTouch

C to 85

library support

acquisition

AVR

8-Bit Microcontroller

C compatible)

(1)

8-bit Atmel

Microcontroller

with 4/8/16/32K

Bytes In-System

Programmable

Flash

ATmega48A

ATmega48PA

ATmega88A

ATmega88PA

ATmega168A

ATmega168PA

ATmega328

ATmega328P

Summary

Rev. 8271DS–AVR–05/11

Related parts for ATmega48A

ATmega48A Summary of contents

Page 1

... Active Mode: 0.2mA – Power-down Mode: 0.1µA – Power-save Mode: 0.75µA (Including 32kHz RTC) ® ® AVR 8-Bit Microcontroller ( compatible) 8-bit Atmel Microcontroller with 4/8/16/32K Bytes In-System Programmable Flash ATmega48A ATmega48PA ATmega88A ATmega88PA ATmega168A ATmega168PA ATmega328 ATmega328P Summary Rev. 8271DS–AVR–05/11 ...

Page 2

... PC1 (ADC1/PCINT9 PC0 (ADC0/PCINT8) 18 GND AREF 6 16 AVCC (PCINT6/XTAL1/TOSC1) PB6 15 PB5 (SCK/PCINT5) 7 (PCINT7/XTAL2/TOSC2) PB7 NOTE: Bottom pad should be soldered to ground. 32UFBGA - Pinout ATmega48A/48PA/88A/88PA/168A/168PA 1 2 PD2 PD1 PC6 PD3 PD4 PD0 GND GND VDD VDD PB6 PD6 PB0 PB7 PD5 PD7 ...

Page 3

... As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. 8271DS–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P ”System Clock and Clock Options” on page Table 29-12 on page ”Alternate Functions of Port B” on page 27 ...

Page 4

... In the TQFP and QFN/MLF package, ADC7:6 serve as analog inputs to the A/D converter. These pins are powered from the analog supply and serve as 10-bit ADC channels. 8271DS–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P , even if the ADC is not used. If the ADC is used, it should be connected ” ...

Page 5

... Overview The ATmega48A/PA/88A/PA/168A/PA/328 low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega48A/PA/88A/PA/168A/PA/328/P achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. ...

Page 6

... Atmel ATmega48A/PA/88A/PA/168A/PA/328 powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega48A/PA/88A/PA/168A/PA/328/P AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Sim- ulators, In-Circuit Emulators, and Evaluation kits ...

Page 7

... ATmega168PA ATmega328 ATmega328P ATmega48A/PA/88A/PA/168A/PA/328/P support a real Read-While-Write Self-Programming mechanism. There is a separate Boot Loader Section, and the SPM instruction can only execute from there. In ATmega 48A/48PA there is no Read-While-Write support and no separate Boot Loader Section. The SPM instruction can execute from the entire Flash. ...

Page 8

... The QTouch Library is FREE and downloadable from the Atmel website at the following location: www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the Atmel QTouch Library User Guide 8271DS–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P 1. ® QTouch ® ...

Page 9

... UDR0 (0xC5) UBRR0H (0xC4) UBRR0L (0xC3) Reserved – (0xC2) UCSR0C UMSEL01 (0xC1) UCSR0B RXCIE0 (0xC0) UCSR0A RXC0 8271DS–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Bit 6 Bit 5 Bit 4 Bit 3 – – – – – – – – – – – – – ...

Page 10

... Reserved – (0x82) TCCR1C FOC1A (0x81) TCCR1B ICNC1 (0x80) TCCR1A COM1A1 (0x7F) DIDR1 – (0x7E) DIDR0 – 8271DS–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Bit 6 Bit 5 Bit 4 Bit 3 – – – – – – TWAM5 TWAM4 TWAM3 TWAM2 TWEA TWSTA TWSTO ...

Page 11

... EEARL 0x20 (0x40) EEDR 0x1F (0x3F) EECR – 0x1E (0x3E) GPIOR0 0x1D (0x3D) EIMSK – 0x1C (0x3C) EIFR – 8271DS–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Bit 6 Bit 5 Bit 4 – – – REFS0 ADLAR – ACME – – ADSC ADATE ADIF ...

Page 12

... Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega48A/PA/88A/PA/168A/PA/328 complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used ...

Page 13

... Branch if T Flag Cleared BRVS k Branch if Overflow Flag is Set BRVC k Branch if Overflow Flag is Cleared 8271DS–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Description Rd ← ← Rdh:Rdl ← Rdh:Rdl + K Rd ← ← ← ← Rdh:Rdl ← Rdh:Rdl - K Rd ← ...

Page 14

... IN Rd Port OUT P, Rr Out Port PUSH Rr Push Register on Stack 8271DS–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Description then PC ← then PC ← I/O(P,b) ← 1 I/O(P,b) ← 0 Rd(n+1) ← Rd(n), Rd(0) ← 0 Rd(n) ← Rd(n+1), Rd(7) ← 0 Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Rd(n) ← Rd(n+1), n=0...6 Rd(3...0)← ...

Page 15

... WDR Watchdog Reset BREAK Break Note: 1. These instructions are only available in ATmega168PA and ATmega328P. 8271DS–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Description Rd ← STACK (see specific descr. for Sleep function) (see specific descr. for WDR/timer) For On-chip Debug Only Operation Flags ...

Page 16

... Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 28P3 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP) 8271DS–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P (2) Ordering Code ATmega48A-AU (5) ATmega48A-AUR ATmega48A-CCU (5) ATmega48A-CCUR (4) ATmega48A-MMH (4)(5) ATmega48A-MMHR ATmega48A-MU (5) ATmega48A-MUR ATmega48A-PU 322. Package Type (1) Package Operational Range 32A 32A 32CC1 32CC1 Industrial 28M1 ° ...

Page 17

... Lead Pitch 0.45mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 32M1-A 32-pad 1.0 body, Lead Pitch 0.50mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 28P3 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP) 8271DS–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P (2) Ordering Code ATmega48PA-AU (5) ATmega48PA-AUR ...

Page 18

Page 19

... Lead Pitch 0.45 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 32M1-A 32-pad 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 28P3 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP) 8271DS–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P (2) Ordering Code ATmega88PA-AU (5) ATmega88PA-AUR ...

Page 20

Page 21

Page 22

... Lead Pitch 0.45mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 28P3 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP) 32M1-A 32-pad 1.0 body, Lead Pitch 0.50mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 8271DS–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P (2) Ordering Code ATmega328-AU (5) ATmega328-AUR ...

Page 23

Page 24

... Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R 8271DS–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P PIN 0° ...

Page 25

... Dimension “b” is measured at the maximum ball dia plane parallel to the seating plane. Note2: Dimension “b1” is the solderable surface defined by the opening of the solder resist layer. Package Drawing Contact: packagedrawings@atmel.com 8271DS–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Pin TOP VIEW E1 e 32-Øb ...

Page 26

... 0.20 b 0.4 Ref BOTTOM VIEW (4x) The terminal # Laser-marked Feature. Note: Package Drawing Contact: packagedrawings@atmel.com 8271DS–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328 TITLE 28M1, 28-pad 1.0 mm Body, Lead Pitch 0.45 mm, 2.4 x 2.4 mm Exposed Pad, Thermally Enhanced Plastic Very Thin Quad Flat No Lead Package (VQFN) ...

Page 27

... TOP VIEW Pin #1 Notch (0. BOTTOM VIEW Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2. 2325 Orchard Parkway San Jose, CA 95131 R 8271DS–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328 TITLE 32M1-A, 32-pad 1.0 mm Body, Lead Pitch 0.50 mm, 3 ...

Page 28

... A SEATING PLANE Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R 8271DS–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P D PIN PLACES 0º ~ 15º REF eB TITLE 28P3, 28-lead (0.300" ...

Page 29

... Errata 11.1 Errata ATmega48A The revision letter in this section refers to the revision of the ATmega48A device. 11.1.1 Rev. D • Analog MUX can be turned off when setting ACME bit 1. Analog MUX can be turned off when setting ACME bit If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in ADMUX is '1' (ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared ...

Page 30

... If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in ADMUX is '1' (ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared. Problem Fix/Workaround Clear the MUX3 bit before setting the ACME bit. 8271DS–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P 30 ...

Page 31

... Problem Fix/Workaround Clear the MUX3 bit before setting the ACME bit. 2. Unstable 32kHz Oscillator The 32kHz oscillator does not work as system clock. The 32kHz oscillator used as asyn- chronous timer is inaccurate. Problem Fix/ Workaround None. 8271DS–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P 31 ...

Page 32

... Problem Fix/ Workaround None. 11.8.4 Rev A • Unstable 32kHz Oscillator 1. Unstable 32kHz Oscillator The 32kHz oscillator does not work as system clock. The 32kHz oscillator used as asyn- chronous timer is inaccurate. Problem Fix/ Workaround None. 8271DS–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P 32 ...

Page 33

... Rev. 8271B – 04/ 8271DS–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Added Atmel QTouch Sensing Capablity Feature Updated ”Register Description” on page 94 Added a footnote to the PINxn, page Updated Updated “Ordering Information”,”ATmega328” on page MMH” and “ATmega328-MMHR”. ...

Page 34

... ATmega48A/PA/88A/PA/168A/PA/328/P New datasheet 8271 with merged information for ATmega48PA, ATmega88PA, ATmega168PA and ATmega48A, ATmega88A andATmega168A. Also included information on ATmega328 and ATmega328P Changes done: – New devices added: ATmega48A/ATmega88A/ATmega168A and ATmega328 – Updated Feature Description – ...

Page 35

... Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Tel: (+49) 89-31970-0 Fax: (+49) 89-3194621 ® and others are registered trademarks or trademarks of Atmel Corporation or its Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 JAPAN Tel: (+81)(3) 3523-3551 Fax: (+81)(3) 3523-7581 8271DS–AVR–05/11 ...

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