ATmega329A Atmel Corporation, ATmega329A Datasheet - Page 272

• Manufacturer Part Number: ATmega329A
• Manufacturer: Atmel Corporation

Specifications of ATmega329A

• Flash (kbytes): 32 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 17
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 100
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Table 26-5.
8284D–AVR–6/11
Step
1
2
3
4
5
6
7
8
9
10
11
Actions
SAMPLE_PR
ELOAD
EXTEST
Verify the
COMP bit
scanned out to
be 0
Verify the
COMP bit
scanned out to
be 1
Algorithm for Using the ADC
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P
• The DAC values must be stable at the midpoint value 0x200 when having the HOLD signal low
As an example, consider the task of verifying a 1.5V ± 5% input signal at ADC channel 3 when
the power supply is 5.0V and AREF is externally connected to V
The recommended values from
in the algorithm in
The column “Actions” describes what JTAG instruction to be used before filling the Boundary-
scan Register with the succeeding columns. The verification should be done on the data
scanned out when scanning in the data on the same row in the table.
Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock fre-
quency. As the algorithm keeps HOLD high for five steps, the TCK clock frequency has to be at
least five times the number of scan bits divided by the maximum hold time, t
ADCEN
(Sample mode).
1
1
1
1
1
1
1
1
1
1
1
The lower limit is:
The upper limit is:
DAC
0x200
0x200
0x200
0x123
0x123
0x200
0x200
0x200
0x143
0x143
0x200
Table
26-5. Only the DAC and port pin values of the Scan Chain are shown.
MUXEN
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
1024 1.5V 0.95 5V
1024 1.5V 1.05 5V
Table 26-4 on page 270
⋅
⋅
HOLD
1
0
1
1
1
1
0
1
1
1
1
⋅
⋅
⁄
⁄
PRECH
=
=
1
1
1
1
0
1
1
1
1
0
1
291
323
are used unless other values are given
=
=
0x123
0x143
PA3.
Data
CC
0
0
0
0
0
0
0
0
0
0
0
.
PA3.
Control
0
0
0
0
0
0
0
0
0
0
0
hold,max
PA3.
Pull-up_
Enable
0
0
0
0
0
0
0
0
0
0
0
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