ATmega3290P Atmel Corporation, ATmega3290P Datasheet

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... Peripheral Features – Segment LCD Driver (ATmega329P) – Segment LCD Driver (ATmega3290P) – Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode – Real Time Counter with Separate Oscillator – ...

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Pin Configurations Figure 1-1. MLF/ Pinout ATmega329P LCDCAP 1 (RXD/PCINT0) PE0 2 (TXD/PCINT1) PE1 3 (XCK/AIN0/PCINT2) PE2 4 (AIN1/PCINT3) PE3 5 (USCK/SCL/PCINT4) PE4 6 (DI/SDA/PCINT5) PE5 7 (DO/PCINT6) PE6 8 (CLKO/PCINT7) PE7 9 (SS/PCINT8) PB0 10 (SCK/PCINT9) PB1 11 ...

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... Figure 1-2. TQFP / Pinout ATmega3290P 1 LCDCAP 2 (RXD/PCINT0) PE0 (TXD/PCINT1) PE1 3 4 (XCK/AIN0/PCINT2) PE2 5 (AIN1/PCINT3) PE3 (USCK/SCL/PCINT4) PE4 6 7 (DI/SDA/PCINT5) PE5 8 (DO/PCINT6) PE6 (CLKO/PCINT7) PE7 9 10 VCC 11 GND 12 DNC 13 (PCINT24/SEG35) PJ0 14 (PCINT25/SEG34) PJ1 15 DNC 16 DNC 17 DNC 18 DNC 19 (SS/PCINT8) PB0 20 (SCK/PCINT9) PB1 21 (MOSI/PCINT10) PB2 ...

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Overview The ATmega329P/3290P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega329P/3290P achieves throughputs approaching 1MIPS per MHz allowing the system designer to optimize ...

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... The ATmega329P/3290P AVR is supported with a full suite of program and system develop- ment tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. 2.2 Comparison between ATmega329P, and ATmega3290P. The ATmega329P, and ATmega3290P differ only in pin count and pinout. summarizes the different configurations for the four devices. Table 2-1. Device ATmega329P ATmega3290P 8021G– ...

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Pin Descriptions The following section describes the I/O-pin special functions. 2.3 Digital supply voltage. 2.3.2 GND Ground. 2.3.3 Port A (PA7...PA0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). ...

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... As inputs, Port J pins that are externally pulled low will source current if the pull-up resistors are activated. The Port J pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port J also serves the functions of various special features of the ATmega3290P as listed on page 87. ...

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RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Characteristics” on page 2.3.13 XTAL1 ...

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Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: 4. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over ...

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AVR CPU Core 6.1 Overview This section discusses the Atmel CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 6.2 Architectural Overview Figure 6-1. ...

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ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three ...

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Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and ...

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General Purpose Register File The Register File is optimized for the Atmel achieve the required performance and flexibility, the following input/output schemes are sup- ported by the Register File: • One 8-bit output operand and one 8-bit result input ...

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The X-register, Y-register, and Z-register The registers R26...R31 have some added functions to their general purpose usage. These reg- isters are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and ...

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SPH and SPL – Stack pointer High and Stack Pointer Low Bit 0x3E (0x5E) 0x3D (0x5D) Read/Write Initial Value 6.7 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The ® Atmel AVR source ...

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Figure 6-5. Register Operands Fetch ALU Operation Execute 6.8 Reset and Interrupt Handling The Atmel Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic ...

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Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be ...

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AVR Memories 7.1 Overview This section describes the different memories in the ATmega329P/3290P. The Atmel architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega329P/3290P features an EEPROM Memory for data ...

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The Atmel than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. ...

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Figure 7-3. 7.4 EEPROM Data Memory The ATmega329P/3290P contains 1Kbytes of data EEPROM memory organized as a sep- arate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least ...

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If a reset occurs while a write operation is in progress, the write operation will be com- pleted provided that the power supply voltage is sufficient. 7.5 I/O Memory The I/O space definition of the ATmega329P/3290P is shown ...

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Register Description 7.6.1 EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access time for the EEPROM is given in lets the user software detect when the next byte can be written. If ...

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EECR – EEPROM Control Register Bit 0x1F (0x3F) Read/Write Initial Value • Bits 7:4 – Reserved These bits are reserved bits and will always read as zero. • Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to ...

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Bit 0 – EERE: EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a ...

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Assembly Code Example EEPROM_write: C Code Example void EEPROM_write(unsigned int uiAddress, unsigned char ucData The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no ...

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Assembly Code Example EEPROM_read: C Code Example unsigned char EEPROM_read(unsigned int uiAddress 7.6.5 GPIOR2 – General Purpose I/O Register 2 Bit 0x2B (0x4B) Read/Write Initial Value 7.6.6 GPIOR1 – General Purpose I/O Register 1 Bit 0x2A (0x4A) Read/Write ...

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System Clock and Clock Options 8.1 Clock Systems and their Distribution Figure 8-1 the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted ...

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Asynchronous Timer Clock – clk The Asynchronous Timer clock allows the Asynchronous Timer/Counter and the LCD controller to be clocked directly from an external clock or an external 32kHz clock crystal. The dedicated clock domain allows using this Timer/Counter ...

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Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively inverting amplifier which can be con- figured for use as an On-chip Oscillator, as shown in ceramic resonator may be used. C1 and C2 should always be ...

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Table 8-4. CKSEL0 Notes: 8.5 Low-frequency Crystal Oscillator The Low-frequency Crystal Oscillator is optimized for use with a 32.768kHz watch crystal. When selecting crystals, load capacitance and crystal’s Equivalent Series Resistance, ESR must be taken ...

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The capacitance (Ce + Ci) needed at each TOSC pin can be calculated by using: where optional external capacitors as described the pin capacitance the load capacitance for a ...

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When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed cali- bration value, see the section Table 8-9. Notes: ...

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Table 8-12. SUT1.. When applying an external clock required to avoid sudden changes in the applied clock fre- quency to ensure stable operation of the MCU. A variation in frequency of more than 2% ...

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Switching Time When switching between prescaler settings, the System Clock Prescaler ensures that no glitches occur in the clock system and that no intermediate frequency is higher than neither the clock frequency corresponding to the previous setting, nor the ...

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Register Description 8.11.1 OSCCAL – Oscillator Calibration Register Bit (0x66) Read/Write Initial Value • Bits 7:0 – CAL7:0: Oscillator Calibration Value The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from ...

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Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE. Interrupts must be disabled when ...

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Power Management and Sleep Modes 9.1 Overview Sleep modes enable the application to shut down unused modules in the MCU, thereby saving- power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the ...

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BOD Disable When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses, the BOD is actively monitoring the power supply voltage during a sleep period. To save power possible to disable the BOD by software for some ...

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USI start condition detection, and the Watchdog continue operating (if enabled). Only an Exter- nal Reset, a Watchdog Reset, a Brown-out Reset, USI start condition interrupt, an external level interrupt on INT0 pin change interrupt can wake up ...

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In all other sleep modes, the clock is already stopped. 9.10 Minimizing Power Consumption There are several possibilities to consider when trying to minimize the power consumption in an AVR ...

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Port Pins When entering a sleep mode, all port pins should be configured to use minimum power. The most important is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clk ...

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Register Description 9.11.1 SMCR – Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. Bit 0x33 (0x53) Read/Write Initial Value • Bits – SM2:0: Sleep Mode Select Bits 2, 1, ...

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Bit 5 – BODSE: BOD Sleep Enable BODSE enables setting of BODS control bit, as explained in BODS bit description. BOD disable is controlled by a timed sequence. 9.11.3 PRR – Power Reduction Register Bit (0x64) Read/Write Initial Value ...

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System Control and Reset 10.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP ...

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Figure 10-1. Reset Logic BODLEVEL [1..0] 10.2.1 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined below the detection level. The POR circuit can be used to ...

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Figure 10-2. MCU Start-up, RESET Tied to V TIME-OUT INTERNAL Figure 10-3. MCU Start-up, RESET Extended Externally TIME-OUT INTERNAL 10.2.2 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the ...

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Brown-out Detection ATmega329P/3290P has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The ...

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Internal Voltage Reference ATmega329P/3290P features an internal bandgap reference. This reference is used for Brown- out Detection, and it can be used as an input to the Analog Comparator or the ADC. 10.3.1 Voltage Reference Enable Signals and Start-up ...

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Figure 10-7. Watchdog Timer 10.4.1 Timed Sequences for Changing the Configuration of the Watchdog Timer The sequence for changing configuration differs slightly between the two safety levels. Separate procedures are described for each level. 10.4.2 Safety Level 1 In this ...

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Register Description 10.5.1 MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset. Bit 0x35 (0x55) Read/Write Initial Value • Bit 4 – JTRF: JTAG Reset Flag This bit is ...

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Bit 3 – WDE: Watchdog Enable When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared ...

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The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. Assembly ...

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Interrupts 11.1 Overview This section describes the specifics of the interrupt handling as performed in Atmel ATmega329P/3290P. For a general explanation of the AVR interrupt handling, refer to and Interrupt Handling” on page 11.2 Interrupt Vectors Table 11-1. Vector ...

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... Flash Section. The address of each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section. 3. PCINT2 and PCINT3 are only present in ATmega3290P. shows reset and Interrupt Vectors placement for the various combinations of Reset and Interrupt Vectors Placement ...

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When the BOOTRST Fuse is unprogrammed, the Boot section size set to 4Kbytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for ...

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Main program start 0x382F/0x782F 0x3830/0x7830 0x3831/0x7831 0x3832/0x7832 0x3833/0x7833 11.2.1 Moving Interrupts Between Application and Boot Space The General Interrupt Control Register controls the placement of the Interrupt Vector table. See ”MCUCR – MCU Control Register” ...

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Assembly Code Example Move_interrupts: ;Get MCUCR in r16, MCUCR mov r17, r16 C Code Example void Move_interrupts(void 11.3 Register Description 11.3.1 MCUCR – MCU Control Register Bit 0x35 (0x55) Read/Write Initial Value • Bit 1 – IVSEL: Interrupt ...

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... Clock and Clock Options” on page Notes: 8021G–AVR–03/11 ”EICRA – External Interrupt Control Register A” on page 1. PCMSK3 and PCMSK2 are only present in ATmega3290P. 2. PCINT30:16 are only present in ATmega3290P. Only PCINT15:0 are present in ATmega329P. See ”Pin Configurations” on page 2 ATmega329P/3290P (1) ...

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Pin Change Interrupt Timing An example of timing of a pin change interrupt is shown in Figure 12-1. Pin Change Interrupt 12.3 Register Description 12.3.1 EICRA – External Interrupt Control Register A The External Interrupt Control Register A contains ...

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Table 12-1. ISC01 12.3.2 EIMSK – External Interrupt Mask Register Bit 0x1D (0x3D) Read/Write Initial Value • Bit 7 – PCIE3: Pin Change Interrupt Enable 3 When the PCIE3 bit is set (one) and the I-bit ...

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EIFR – External Interrupt Flag Register Bit 0x1C (0x3C) Read/Write Initial Value • Bit 7 – PCIF3: Pin Change Interrupt Flag 3 When a logic change on any PCINT30:24 pin triggers an interrupt request, PCIF3 becomes set (one). If ...

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... PCINT30 PCINT29 PCINT28 R R PCINT23 PCINT22 PCINT21 PCINT20 R/W R/W R PCMSK3 and PCMSK2 are only present in ATmega3290P PCINT15 PCINT14 PCINT13 PCINT12 R/W R/W R PCINT7 PCINT6 PCINT5 PCINT4 R/W R/W R/W R ATmega329P/3290P ...

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I/O-Ports 13.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with ...

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Functions” on page nate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 13.2 Ports as General Digital I/O The ...

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The port pins are tri-stated when reset condition becomes active, even if no clocks are running. If PORTxn is written logic one when the pin is configured as an output pin, the port pin ...

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Figure 13-3. Synchronization when Reading an Externally Applied Pin value INSTRUCTIONS Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the ...

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Assembly Code Example C Code Example unsigned char i; Note: 13.2.5 Digital Input Enable and Sleep Modes As shown in Schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Power-save mode, ...

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Unconnected Pins If some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, float- ing inputs ...

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Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. shows how the port pin control signals from the simplified alternate functions. The overriding signals may not be present in all port pins, ...

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... The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details. Some pins are connected to different LCD segments on ATmega329P and ATmega3290P. See pinout ”MLF/ Pinout ATmega329P” on page 2 8021G– ...

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Alternate Functions of Port A The Port A has an alternate function as COM0:3 and SEG0:3 for the LCD Controller. Table 13-3. Port Pin PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Table 13-4 shown in Table 13-4. Signal ...

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Table 13-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 13.3.2 Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 13-6. Port Pin PB7 PB6 PB5 PB4 PB3 ...

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OC1B/PCINT14, Bit 6 OC1B, Output Compare Match B output: The PB6 pin can serve as an external output for the Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDB6 set (one)) to serve this ...

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When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB0. When the pin is forced input, the pull-up can still be controlled by the PORTB0 bit PCINT8, Pin ...

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Alternate Functions of Port C The Port C has an alternate function as SEG for the LCD Controller. Table 13-9. Port Pin PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 The alternate pin configuration is as follows: • SEG ...

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Table 13-11. Overriding Signals for Alternate Functions in PC3:PC0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 13.3.4 Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 13-12. ...

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Table 13-13 shown in Table 13-13. Overriding Signals for Alternate Functions PD7:PD4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO AIO Table 13-14. Overriding Signals for Alternate Functions in PD3:PD0 Signal Name PUOE PUOV DDOE ...

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Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 13-15. Port E Pins Alternate Functions Port Pin PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 • PCINT7 – Port E, Bit 7 ...

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XCK/AIN0/PCINT2 – Port E, Bit 2 XCK, USART0 External Clock. The Data Direction Register (DDE2) controls whether the clock is output (DDE2 set) or input (DDE2 cleared). The XCK pin is active only when the USART0 oper- ates in ...

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Table 13-17. Overriding Signals for Alternate Functions in PE3:PE0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Note: 13.3.6 Alternate Functions of Port F The Port F has an alternate function as analog input for ...

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TDO, ADC6 – Port F, Bit 6 ADC6, Analog to Digital Converter, Channel 6 TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When the JTAG interface is enabled, this pin can not be ...

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Table 13-20. Overriding Signals for Alternate Functions in PF3:PF0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 13.3.7 Alternate Functions of Port G The alternate pin configuration is as follows: Table 13-21. Port G Pins ...

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SEG – Port G, Bit 2 SEG, LCD front plane 4/4. • SEG – Port G, Bit 1 SEG, Segment driver 17/13. • SEG – Port G, Bit 0 SEG, LCD front plane 18/14. Table 13-21 shown in Table ...

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... DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO AIO 13.3.8 Alternate Functions of Port H Port H is only present in ATmega3290P. The alternate pin configuration is as follows: Table 13-24. Port H Pins Alternate Functions Port Pin PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 The alternate pin configuration is as follows: • ...

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PCINT22/SEG – Port H, Bit 6 PCINT22, Pin Change Interrupt Source 22: The PH6 pin can serve as an external interrupt source. SEG, LCD front plane 37. • PCINT21/SEG – Port H, Bit 5 PCINT21, Pin Change Interrupt Source ...

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Table 13-25 shown in Table 13-25. Overriding Signals for Alternate Functions in PH7:4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO AIO Table 13-26. Overriding Signals for Alternate Functions in PH3:0 (ATmega329P/3290P) Signal Name PUOE ...

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... Alternate Functions of Port J Port J is only present in ATmega3290P. The alternate pin configuration is as follows: Table 13-27. Port J Pins Alternate Functions Port Pin PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 The alternate pin configuration is as follows: • PCINT30/SEG – Port J, Bit 6 PCINT30, Pin Change Interrupt Source 30: The PE30 pin can serve as an external interrupt source ...

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PCINT28/SEG – Port J, Bit 4 PCINT28, Pin Change Interrupt Source 28: The PE28 pin can serve as an external interrupt source. SEG, LCD front plane 29. • PCINT27/SEG – Port J, Bit 3 PCINT27, Pin Change Interrupt Source ...

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Table 13-29. Overriding Signals for Alternate Functions in PH3:0 (ATmega329P/3290P) Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 8021G–AVR–03/11 PJ3/PCINT27/ PJ2/PCINT26/ SEG30 SEG31 LCDEN LCDEN 0 0 LCDEN LCDEN ...

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Register Description 13.4.1 MCUCR – MCU Control Register Bit 0x35 (0x55) Read/Write Initial Value • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the ...

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PORTC – Port C Data Register Bit 0x08 (0x28) Read/Write Initial Value 13.4.9 DDRC – Port C Data Direction Register Bit 0x07 (0x27) Read/Write Initial Value 13.4.10 PINC – Port C Input Pins Address Bit 0x06 (0x26) Read/Write Initial ...

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PINE – Port E Input Pins Address Bit 0x0C (0x2C) Read/Write Initial Value 13.4.17 PORTF – Port F Data Register Bit 0x11 (0x31) Read/Write Initial Value 13.4.18 DDRF – Port F Data Direction Register Bit 0x10 (0x30) Read/Write Initial ...

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... PORTJ6 PORTJ5 R R – DDJ6 DDJ5 R R – PINJ6 PINJ5 R R/W R/W 0 N/A N/A 1. Register only available in ATmega3290P. ATmega329P/3290P DDH4 DDH3 DDH2 DDH1 R/W R/W R/W R PINH4 PINH3 PINH2 PINH1 R/W R/W R/W R/W N/A N/A N/A N PORTJ4 ...

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... TCCRn count clear Control Logic direction BOTTOM TOP Timer/Counter TCNTn = OCRn ATmega329P/3290P Figure 14-1. For the actual placement and ”TQFP / Pinout ATmega3290P” ”Register Description” on page Clock Select clk Tn Edge Detector ( From Prescaler ) 0xFF Waveform Generation TOVn (Int.Req.) Tn OCn (Int.Req.) OCn ) ...

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The double buffered Output Compare Register (OCR0A) is compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to gener- ate a PWM or variable frequency output on the Output ...

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Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02 the timer ...

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Output Compare Unit The 8-bit comparator continuously compares TCNT0 with the Output Compare Register (OCR0A). Whenever TCNT0 equals OCR0A, the comparator signals a match. A match will set the Output Compare Flag (OCF0A) at the next timer clock cycle. ...

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Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC0A) bit. Forcing compare match will not set the OCF0A Flag or reload/clear ...

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Figure 14-4. Compare Match Output Unit, Schematic The general I/O port function is overridden by the Output Compare (OC0A) from the Waveform Generator if either of the COM0A1:0 bits are set. However, the OC0A pin direction (input or out- put) ...

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Normal Mode The simplest mode of operation is the Normal mode (WGM01:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum ...

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The waveform generated will have a maximum frequency when OCR0A is set to zero (0x00). The waveform frequency is defined by the following clk_I/O equation: The N variable represents the ...

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In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin. Setting the COM0A1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM0A1:0 to ...

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Figure 14-7. Phase Correct PWM Mode, Timing Diagram TCNTn OCn OCn Period The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches ...

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BOTTOM the OCn value at MAX must correspond to the result of an up- counting Compare Match. • The timer starts counting from a value higher than the one in OCR0A, and for that reason misses the Compare ...

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Figure 4 Figure 4. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (f /8) clk_I/O clk clk (clk TCNTn (CTC) OCRnx OCFnx 8021G–AVR–03/11 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode. I/O ...

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... However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT1 for accessing Timer/Counter1 counter value and so on. A simplified block diagram of the 16-bit Timer/Counter is shown in placement of I/O pins, refer to ATmega3290P” on page shown in bold. The device-specific I/O Register and bit locations are listed in the Description” on page The PRTIM1 bit in Timer/Counter1 module. 8021G– ...

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Figure 15-1. 16-bit Timer/Counter Block Diagram Note: 15.2.1 Registers The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Regis- ter (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16- bit registers. These procedures are ...

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Compare Units” on page Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge trig- gered) event on either the Input Capture ...

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Accessing 16-bit Registers The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit ...

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The following code examples show how atomic read of the TCNT1 Register contents. Reading any ...

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The following code examples show how atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example TIM16_WriteTCNT1: C Code Example void ...

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Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 15-2 Figure 15-2. Counter Unit Block Diagram Signal description (internal signals): Count Direction Clear clk TOP BOTTOM The 16-bit counter is mapped ...

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The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt. 15.6 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can ...

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TOP value can be written to the ICR1 Register. When writing the ICR1 Register the high byte must be written to the ICR1H I/O location before the low byte is written ...

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I/O bit location). For measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is used). 15.7 Output Compare Units The 16-bit comparator continuously compares ...

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PWM pulses, thereby making the out- put glitch-free. The OCR1x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR1x Buffer ...

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Compare Match Output Unit The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match. Secondly the COM1x1:0 bits control the OC1x ...

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OC1x Register performed on the next compare match. For compare output actions in the non-PWM modes refer to page 128, and for phase correct and phase and frequency correct PWM refer to page 128. A change of ...

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Figure 15-6. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 Flag according to the register used to define ...

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The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the max- imum resolution is 16-bit ...

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When the OCR1A I/O location is written the value written will be put into the OCR1A Buffer Register. The OCR1A Compare Register will then be updated with the value in the Buffer Register at the next ...

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OCR1A set to MAX). The PWM resolu- tion in bits can be calculated by using the following equation: In phase correct PWM mode the counter is incremented until the counter value ...

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Since the OCR1x update occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of the falling slope is determined by the previous TOP value, while the length of the rising slope is ...

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In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The counter has then reached the TOP and ...

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PWM frequency is actively changed by changing the TOP value, using the OCR1A as TOP is clearly a better choice due to its double buffer feature. In phase and frequency correct PWM mode, the compare units allow ...

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Figure 15-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f Figure 15-12 frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by ...

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Figure 15-13. Timer/Counter Timing Diagram, with Prescaler (f and ICF n 15.11 Register Description 15.11.1 TCCR1A – Timer/Counter1 Control Register A Bit (0x80) Read/Write Initial Value • Bit 7:6 – COM1A1:0: Compare Output Mode for Unit A • Bit 5:4 ...

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Table 15-3 PWM mode. Table 15-3. COM1A1/COM1B1 Note: Table 15-4 correct or the phase and frequency correct, PWM mode. Table 15-4. COM1A1/COM1B1 Note: • Bit 1:0 – WGM11:0: Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B ...

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Table 15-5. Waveform Generation Mode Bit Description WGM12 Mode WGM13 (CTC1) (PWM11 ...

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When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Cap- ture function is disabled. • Bit 5 – Reserved ...

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A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero. 15.11.4 TCNT1H and TCNT1L – Timer/Counter1 ...

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ICR1H and ICR1L – Input Capture Register 1 Bit (0x87) (0x86) Read/Write Initial Value The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator ...

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TIFR1 – Timer/Counter1 Interrupt Flag Register Bit 0x16 (0x36) Read/Write Initial Value • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register ...

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Timer/Counter0 and Timer/Counter1 Prescalers Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. 16.0.1 Internal Clock Source The Timer/Counter can be clocked directly ...

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Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system clock cycle, otherwise risk that a false Timer/Counter clock pulse is generated. Each half period of the ...

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Register Description 16.1.1 TCCR0A – Timer/Counter Control Register A Bit 0x24 (0x44) Read/Write Initial Value • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM00 bit specifies a non-PWM mode. However, ...

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Table 16-2. COM0A1 Table 16-3 mode. Table 16-3. COM0A1 Note: Table 16-4 rect PWM mode. Table 16-4. COM0A1 Note: 8021G–AVR–03/11 Compare Output Mode, non-PWM Mode COM0A0 Description 0 ...

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Bit 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 16-5. CS02 external pin modes are used for ...

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TIMSK0 – Timer/Counter 0 Interrupt Mask Register Bit (0x6E) Read/Write Initial Value • Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable When the OCIE0A bit is written to one, and the I-bit in the Status Register ...

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GTCCR – General Timer/Counter Control Register Bit 0x23 (0x43) Read/Write Initial Value • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written ...

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... Control Logic direction BOTTOM Timer/Counter TCNTn = OCRnx Synchronized Status flags Status flags ASSRn ATmega329P/3290P Figure 17-1. For the actual placement and ”TQFP / Pinout ATmega3290P” ”Register Description” on page TCCRnx clk Tn TOP T/C Oscillator Prescaler 0xFF OCnx (Int.Req.) Waveform Generation Synchronization Unit asynchronous mode ...

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All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK2). TIFR2 and TIMSK2 are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2 pins, as detailed ...

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Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. 17-2 shows a block diagram of the counter and its surrounding environment. Figure 17-2. Counter Unit Block Diagram Signal description (internal signals): count direction ...

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Generator for handling the special cases of the extreme values in some modes of operation. See ”Modes of Operation” on page Figure 17-3 Figure 17-3. Output Compare Unit, Block Diagram The OCR2A Register is double buffered when using any of ...

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Using the Output Compare Unit Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT2 when using the Output Compare unit, independently of whether ...

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Register bit for the OC2A pin (DDR_OC2A) must be set as output before the OC2A value is vis- ible on the pin. The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin ...

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The timing diagram for the CTC mode is shown in increases until a compare match occurs between TCNT2 and OCR2A, and then counter (TCNT2) is cleared. Figure 17-5. CTC Mode, Timing Diagram TCNTn OCnx (Toggle) Period An interrupt can be ...

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DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the MAX value. The ...

Page 149

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set- ting OC2A to toggle its logical level on each compare match (COM2A1:0 = 1). The waveform generated will have a maximum frequency of ...

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In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2A pin. Setting the COM2A1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM2A1:0 to ...

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Figure 17-9 Figure 17-9. Timer/Counter Timing Diagram, with Prescaler (f Figure 17-10 Figure 17-10. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (f Figure 17-11 8021G–AVR–03/11 shows the same timing data, but with the prescaler enabled. clk I/O clk Tn ...

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Figure 17-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- 17.9 Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer ...

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Power-save or ADC Noise Reduction mode is sufficient, the following algorithm can be used to ensure that one TOSC1 cycle has elapsed: 1. Write a value to TCCR2A, TCNT2, or OCR2A. ...

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Timer/Counter Prescaler Figure 17-12. Prescaler for Timer/Counter2 TOSC1 The clock source for Timer/Counter2 is named clk system I/O clock clk clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter (RTC). When AS2 is ...

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Register Description 17.10.1 TCCR2A – Timer/Counter Control Register A Bit (0xB0) Read/Write Initial Value • Bit 7 – FOC2A: Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ...

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When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the WGM21:0 bit setting. are set to a normal or CTC mode (non-PWM). Table 17-3. COM2A1 Table 17-4 mode. Table 17-4. COM2A1 ...

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Table 17-6. CS22 17.10.2 TCNT2 – Timer/Counter Register Bit (0xB2) Read/Write Initial Value The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing ...

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Bit 3 – AS2: Asynchronous Timer/Counter2 When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clk written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the Timer Oscil- lator 1 (TOSC1) pin. ...

Page 159

TIFR2 – Timer/Counter2 Interrupt Flag Register Bit 0x17 (0x37) Read/Write Initial Value • Bit 1 – OCF2A: Output Compare Flag 2 A The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the data ...

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SPI – Serial Peripheral Interface 18.1 Features • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of Transmission Interrupt Flag • Write ...

Page 161

The interconnection between Master and Slave CPUs with SPI is shown in 161. The system consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin ...

Page 162

When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Functions” on page Table 18-1. Pin MOSI MISO SCK SS Note: 8021G–AVR–03/11 Table 18-1. For more details on automatic port ...

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The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and ...

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The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example SPI_SlaveInit: SPI_SlaveReceive: C Code Example void SPI_SlaveInit(void char SPI_SlaveReceive(void Note: 8021G–AVR–03/11 (1) ; ...

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SS Pin Functionality 18.3.1 Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so ...

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Figure 18-3. SPI Transfer Format with CPHA = 0 Figure 18-4. SPI Transfer Format with CPHA = 1 8021G–AVR–03/11 SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 ...

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Register Description 18.5.1 SPCR – SPI Control Register Bit 0x2C (0x4C) Read/Write Initial Value • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is ...

Page 168

Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between ...

Page 169

SPDR – SPI Data Register Bit 0x2E (0x4E) Read/Write Initial Value The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. ...

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USART0 19.1 Features • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with ...

Page 171

Figure 19-1. USART Block Diagram Note: The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units. The Clock Generation ...

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AVR USART vs. AVR UART – Compatibility The USART is fully compatible with the AVR UART regarding: • Bit locations inside all USART Registers. • Baud Rate Generation. • Transmitter Operation. • Transmit Buffer Functionality. • Receiver Operation. However, ...

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Figure 19-2. .Clock Generation Logic, Block Diagram Signal description: txclk rxclk xcki xcko fosc 19.3.1 Internal Clock Generation – The Baud Rate Generator Internal clock generation is used for the asynchronous and the synchronous master modes of operation. The description ...

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Figure 19-3. Equations for Calculating Baud Rate Register Setting Operating Mode Asynchronous Normal mode (U2Xn = 0) Asynchronous Double Speed mode (U2Xn = 1) Synchronous Master mode Note: BAUD f OSC UBRRn Some examples of UBRRn values for some system ...

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Synchronous Clock Operation When synchronous mode is used (UMSELn = 1), the XCK pin will be used as either clock input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or data change is ...

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St ( IDLE The frame format used by the USART is set by the UCSZn2:0, UPMn1:0 and USBSn bits in UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting. Note that changing the setting of any ...

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For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 Registers. Assembly Code Example USART_Init: C Code Example #define FOSC 1843200 // Clock Speed #define BAUD 9600 #define MYUBRR FOSC/16/BAUD-1 void main( void ) ...

Page 178

Data Transmission – The USART Transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXENn) bit in the UCSRnB Register. When the Transmitter is enabled, the normal port operation of the TxD pin is overrid- den by ...

Page 179

Sending Frames with 9 Data Bit If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8n bit in UCSRnB before the low byte of the character is written to UDRn. The following ...

Page 180

Shift Register. For compat- ibility with future devices, always write this bit to zero when writing the UCSRnA Register. When the Data Register Empty Interrupt Enable (UDRIEn) ...

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UDRn will be masked to zero. The USART has to be initialized before the function can be used. Assembly Code Example USART_Receive: C Code Example unsigned char USART_Receive( void ) { } Note: ...

Page 182

The following code example shows a simple USART receive function that handles both nine bit characters and the status bits. Assembly Code Example USART_Receive: USART_ReceiveNoError: C Code Example unsigned int USART_Receive( void ) { } Note: The receive function example ...

Page 183

Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buf- fer. This flag is one when unread ...

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The Parity Error (UPEn) Flag can then be read by software to check if the frame had a Parity Error. The UPEn bit is set if the next character that can be read ...

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Double Speed mode (U2Xn = 1) of operation. Samples denoted zero are samples done when the RxD line is idle (i.e., no communication activity). Figure 19-6. Start Bit Sampling When the clock recovery logic ...

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Figure 19-8. Stop Bit Sampling and Next Start Bit Sampling The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 ...

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Table 19-1. # (Data+Parity Bit) Table 19-2. # (Data+Parity Bit) The recommendations of the maximum receiver baud rate error was made under the assump- tion that the Receiver and Transmitter equally divides the maximum total error. There are two possible ...

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When the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. When the frame type bit ...

Page 189

Register Description 19.10.1 UDRn – USART I/O Data Register n Bit Read/Write Initial Value The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDRn. ...

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Bit 5 – UDREn: USART Data Register Empty The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn is one, the buffer is empty, and therefore ready to be written. The UDREn ...

Page 191

Bit 6 – TXCIEn: TX Complete Interrupt Enable Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete interrupt will be generated only if the TXCIEn bit is written to one, the Global Interrupt ...

Page 192

Bit 5:4 – UPMn1:0: Parity Mode These bits enable and set type of parity generation and check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will ...

Page 193

Figure 19-13. UCPOLn Bit Settings 19.10.5 UBRRnL and UBRRnH – USART Baud Rate Registers n Bit Read/Write Initial Value • Bit 15:12 – Reserved Bits These bits are reserved for future use. For compatibility with future devices, these bit must ...

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Table 19-3. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies f = 1.0000 MHz osc Baud U2Xn = 0 Rate (bps) UBRRn Error UBRRn 2400 25 0.2% 51 4800 12 0.2% 25 9600 6 -7.0% 12 14.4k 3 8.5% ...

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Table 19-4. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 3.6864MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRRn Error UBRRn 2400 95 0.0% 191 4800 47 0.0% 95 9600 23 0.0% 47 ...

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Table 1. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 8.0000MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRRn Error UBRRn 2400 207 0.2% 416 4800 103 0.2% 207 9600 51 0.2% 103 ...

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Table 2. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 16.0000MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRRn Error UBRRn 2400 416 -0.1% 832 4800 207 0.2% 416 9600 103 0.2% 207 ...

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... CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The 3 2 USIDR 4-bit Counter 1 0 USISR 2 USICR ATmega329P/3290P and ”TQFP / Pinout ATmega3290P” on ”Register Description” on page DI/SDA TIM0 COMP 0 USCK/SCL 1 CLOCK HOLD [1] Two-wire Clock Control Unit (Output only) ...

Page 199

The 4-bit counter can be both read and written via the data bus, and can generate an overflow interrupt. Both the Serial Register and the counter are clocked simultaneously by the same clock source. This allows the counter to count ...

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Figure 20-3. Three-wire Mode, Timing Diagram CYCLE USCK USCK The Three-wire mode timing is shown in Figure 20-3. At the top of the figure is a USCK cycle ref- erence. One bit is shifted into the USI Shift Register (USIDR) ...