ATmega165P Atmel Corporation, ATmega165P Datasheet - Page 242
ATmega165P
Manufacturer Part Number
ATmega165P
Description
Manufacturer
Atmel Corporation
Specifications of ATmega165P
Flash (kbytes)
16 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
17
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATmega165PV-8AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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23.6
8019K–AVR–11/10
ATmega165P Boundary-scan Order
Table 23-4.
Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock fre-
quency. As the algorithm keeps HOLD high for five steps, the TCK clock frequency has to be at
least five times the number of scan bits divided by the maximum hold time, t
Table 23-5
selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The
scan order follows the pin-out order as far as possible. Therefore, the bits of Port A is scanned in
the opposite bit order of the other ports. Exceptions from the rules are the Scan chains for the
analog circuits, which constitute the most significant bits of the scan chain regardless of which
physical pin they are connected to. In
PXn. Control corresponds to FF1, and PXn. Pull-up_enable corresponds to FF2. Bit 4, bit 5, bit
6, and bit 7 of Port F is not in the scan chain, since these pins constitute the TAP pins when the
JTAG is enabled.
Table 23-5.
Step
1
2
3
4
5
6
7
8
9
10
11
Bit Number
197
196
195
194
Actions
SAMPLE_P
RELOAD
EXTEST
Verify the
COMP bit
scanned out
to be 0
Verify the
COMP bit
scanned out
to be 1
shows the Scan order between TDI and TDO when the Boundary-scan chain is
Algorithm for Using the ADC
ATmega165P Boundary-scan Order
Signal Name
AC_IDLE
ACO
ACME
AINBG
ADCEN
1
1
1
1
1
1
1
1
1
1
1
DAC
0x200
0x200
0x200
0x123
0x123
0x200
0x200
0x200
0x143
0x143
0x200
Figure 23-3 on page
MUXEN
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
HOLD
1
0
1
1
1
1
0
1
1
1
1
Module
Comparator
233, PXn. Data corresponds to FF0,
PRECH
1
1
1
1
0
1
1
1
1
0
1
PA3.
Data
ATmega165P
0
0
0
0
0
0
0
0
0
0
0
hold,max
PA3.
Control
0
0
0
0
0
0
0
0
0
0
0
PA3.
Pull-up_
Enable
0
0
0
0
0
0
0
0
0
0
0
242
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