ATmega128RZBV Atmel Corporation, ATmega128RZBV Datasheet - Page 163

• Manufacturer Part Number: ATmega128RZBV
• Manufacturer: Atmel Corporation

Specifications of ATmega128RZBV

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 16 MHz
• Max I/o Pins: 86
• Spi: 5
• Twi (i2c): 1
• Uart: 4
• Adc Channels: 16
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: No
• Sram (kbytes): 8
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 6
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 0.25
• Antenna Diversity: No
• External Pa Control: No
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 16.0
• Transmit Current Consumption (ma): 17.0
• Link Budget (dbm): 104

17.11.15 TCNT4H and TCNT4L –Timer/Counter 4
17.11.16 TCNT5H and TCNT5L –Timer/Counter 5
17.11.17 OCR1AH and OCR1AL – Output Compare Register 1 A
17.11.18 OCR1BH and OCR1BL – Output Compare Register 1 B
17.11.19 OCR1CH and OCR1CL – Output Compare Register 1 C
2549N–AVR–05/11
The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give direct
access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To
ensure that both the high and low bytes are read and written simultaneously when the CPU
accesses these registers, the access is performed using an 8-bit temporary High Byte Register
(TEMP). This temporary register is shared by all the other 16-bit registers.
Registers” on page 138.
Modifying the counter (TCNTn) while the counter is running introduces a risk of missing a com-
pare match between TCNTn and one of the OCRnx Registers.
Writing to the TCNTn Register blocks (removes) the compare match on the following timer clock
for all compare units.
Bit
(0xA5)
(0xA4)
Read/Write
Initial Value
Bit
(0x125)
(0x124)
Read/Write
Initial Value
Bit
(0x89)
(0x88)
Read/Write
Initial Value
Bit
(0x8B)
(0x8A)
Read/Write
Initial Value
Bit
(0x8D)
(0x8C)
Read/Write
Initial Value
R/W
R/W
R/W
R/W
R/W
7
0
7
0
7
0
7
0
7
0
R/W
R/W
R/W
R/W
R/W
6
0
6
0
6
0
6
0
6
0
ATmega640/1280/1281/2560/2561
R/W
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
5
0
R/W
R/W
R/W
R/W
R/W
4
0
4
0
4
0
4
0
4
0
OCR1A[15:8]
OCR1B[15:8]
OCR1C[15:8]
TCNT4[15:8]
TCNT5[15:8]
OCR1A[7:0]
OCR1B[7:0]
OCR1C[7:0]
TCNT4[7:0]
TCNT5[7:0]
R/W
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
3
0
R/W
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
2
0
R/W
R/W
R/W
R/W
R/W
1
0
1
0
1
0
1
0
1
0
See “Accessing 16-bit
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
OCR1AH
OCR1BH
OCR1CH
OCR1AL
OCR1BL
OCR1CL
TCNT4H
TCNT4L
TCNT5H
TCNT5L
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