ATmega1284P Atmel Corporation, ATmega1284P Datasheet - Page 139
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ATmega1284P
Manufacturer Part Number
ATmega1284P
Description
Manufacturer
Atmel Corporation
Specifications of ATmega1284P
Flash (kbytes)
128 Kbytes
Pin Count
44
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
32
Usb Speed
No
Usb Interface
No
Spi
3
Twi (i2c)
1
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Eeprom (bytes)
4096
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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16.11.13 TIMSK3 – Timer/Counter3 Interrupt Mask Register
16.11.14 TIFR1 – Timer/Counter1 Interrupt Flag Register
8272C–AVR–06/11
• Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector
(See Section “11.3” on page
• Bit 7:6 – Reserved
These bits are unused and will always read as zero.
• Bit 5 – ICIE3: Timer/Counter3, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt
Vector (See “Interrupts” on page 61) is executed when the ICF3 Flag, located in TIFR3, is set.
• Bit 4:3 – Reserved
These bits are unused and will always read as zero.
• Bit 2 – OCIE3B: Timer/Counter3, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter3 Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector (See “Interrupts” on page 61) is executed when the OCF3B Flag, located in
TIFR3, is set.
• Bit 1 – OCIE3A: Timer/Counter3, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter3 Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector (See “Interrupts” on page 61) is executed when the OCF3A Flag, located in
TIFR3, is set.
• Bit 0 – TOIE3: Timer/Counter3, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter3 Overflow interrupt is enabled. The corresponding Interrupt Vector
(See “Watchdog Timer” on page 55) is executed when the TOV3 Flag, located in TIFR3, is set.
• Bit 7:6 – Reserved
These bits are unused and will always read as zero.
Bit
(0x71)
Read/Write
Initial Value
Bit
0x16 (0x36)
Read/Write
Initial Value
ATmega164A/PA/324A/PA/644A/PA/1284/P
R
R
7
–
0
7
–
0
R
6
–
0
R
6
–
0
55) is executed when the TOV1 Flag, located in TIFR1, is set.
ICIE3
R/W
ICF1
R/W
5
0
5
0
R
4
–
0
R
4
–
0
R
3
–
0
R
3
–
0
OCIE3B
OCF1B
R/W
R/W
2
0
2
0
OCIE3A
OCF1A
R/W
R/W
1
0
1
0
TOIE3
TOV1
R/W
R/W
0
0
0
0
TIMSK3
TIFR1
139
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