AT90PWM3B Atmel Corporation, AT90PWM3B Datasheet - Page 24

• Manufacturer Part Number: AT90PWM3B
• Manufacturer: Atmel Corporation

Specifications of AT90PWM3B

• Flash (kbytes): 8 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 27
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 105
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 1
• Pwm Channels: 12
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

24
AT90PWM2/3/2B/3B
5. PSC: Output Polarity in Centered Mode
6. PSC : POACnA/B Output Activity
7. VREF
8. DALI
9. DAC: Register Update
10. DAC : Output spikes
11. DAC driver: Output Voltage linearity
12. ADC : Conversion accuracy
13. Analog comparator: Offset value
14. Analog comparator: Output signal
In centered mode, PSCOUTn1 outputs are not inverted, so they are active at the same time
as PSCOUTn0.
Workaround:
Use an external inverter (or a driver with inverting output) to drive the load on
PSCOUTn1.
These register bits are not implemented in rev A.
Workaround:
Do not use this feature.
Remark: To have Internal Vref on AREF pin select an internal analog feature such as DAC
or ADC.
Some stand by power consuption may be observed if Vref equals AVcc
Some troubles on Dali extension when edges are not symmetric.
Workaround:
Use an optocoupler providing symmetric edges on Rx and Tx DALI lines (only recom-
manded for software validation purpose).
Registers DACL & DACH are not written when the DAC is not enabled.
Workaround:
Enable DAC with DAEN before writing in DACL & DACH. To prevent an unwanted zero out-
put on DAC pin, enable DAC output, with DAOE afterwards.
During transition between two codes, a spike may appears
Work around:
Filter spike or wait for steady state
No spike appears if the 4 last signifiant bits remain zero.
The voltage linearity of the DAC driver is limited when the DAC output goes above Vcc - 1V.
Work around:
Do not use AVcc as Vref ; internal Vref gives good results
The conversion accuracy degrades when the ADC clock is 1 & 2 MHz.
Work around:
When a 10 bit conversion accuracy is required, use an ADC clock of 500 kHz or below.
The offset value increases when the common mode voltage is above Vcc - 1.5V.
Work around:
Limit common mode voltage
4317JS–AVR–08/10